ManUfacturability, Test, and Diagnostics for Microelectronics

1
ManUfacturability, Test, and Diagnostics for
Microelectronics

• Summer Semester 2008Dr. Bernd KoenemannProf.
  Dr. Walter Anheier

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Overall Context
3
Whats the Problem?
Perfectby design ???
Lost inTranslation
Defects !!!
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Layout

• The logic and/or analog design structures must be
  translated into geometrical shapes and layers for
  mask making

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CMOS NAND-Gate
Source D. Pan, University of Texas
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Full Custom Design Style
Source D. Pan, University of Texas
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Standard Cell Design Style
Source D. Pan, University of Texas
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Gate Array Design Style
VDD
Metal1
Metal2
Structured ASICs (hot topics nowadays) are
essentially gate array
Source D. Pan, University of Texas
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FPGA Design Style
Source D. Pan, University of Texas
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Scaling Roadmap
Source ITRS 2001
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Metal Stack
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Defect Types and Potential Sources
Static
Environmental (Vdd, T, PLL, SEU)Coupling Noise,
Signal IntegrityHotE, Electromigration, Negative
Bias Threshold Instability (NBTI)
? Particle and otherSingle Event Upsets (SEU)
Dynamic
From R.Puri, IBM
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Spot Defects Particles

• Caused by dirt/impurities, and/or
  equipment/material problems
• E.g., particle contamination causes a short
• May be visible to in-line inspection tools
• Can be characterized by test structures
• Create catastrophic or parametric defects
• Area-sensitive (critical area)

From Skumanich and Ryabova, ASMC 2002
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Critical Area Concept

• Area into which defect center must fall to create
• Shorts for additive material, opens for
  subtractive material

CA for additive material
CA for subtractive material
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Critical Area Example
From Christie, P. de Gyvez
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Critical Area and Yield

• Particle-size distribution and defect types must
  be taken into account
• Monte-Carlo simulation
• Analytical methods

Layout Defect Sensitivity
Probability of Failure
0.35
1.2
0.3
1
0.25
0.8
0.2
Sensitivity
0.6
pdf
0.15
0.1
0.4
0.05
0.2
0
0
1
3
5
7
9
11
13
15
17
19
1
4
7
1
4
0.4
0.7
1.3
1.6
1.9
2.2
2.5
2.8
3.1
3.4
3.7
10
13
16
19
22
25
28
31
34
37
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Defect size (10um)
Defect size
Defect size
From Christie, P. de Gyvez
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Feature-Based Yield
Particle Defect-driven vs. Feature-driven
Yield Failure to form features replaces particle
defects as the problem
100
Traditional defect-limitedyield
90
Product yield
80
70
60
0.8?m
0.5?m
0.35?m
0.25?m
.18?m
.13?m
90nm
From PDF Solutions
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Sub-Wavelength Lithography
Lithography
Lithography
365nm
365nm
Wavelength
Wavelength
248nm
248nm
193nm
193nm
180nm
180nm
130nm
130nm
90nm
90nm
65nm
65nm
FeatureSize
45nm
45nm
32nm
32nm
13nm
13nm
EUV
EUV
1980
1990
2000
2010
2020
Source Borkar et al., GVLSI 2002 Grobman, DAC
2001
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Photo Lithography
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Photo Lithographic Process
Source D. Pan, University of Texas
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Printing Effects
Source Synopsys
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Optical Proximity Effects

• Optical Proximity Correction (OPC) mitigates
  problem but is very complex

Original Layout 0.18 mm
Silicon Image
Image from Pati, DAC99
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Layout vs. Post-OPC Silicon Shapes

• Affects performance, checking, parasitics/extracti
  on

From Rencher and Schellenberg, EE Design, 2003
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OPE/OPC Example
Image from B. Cory
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Impact of OPE/OPC

• Affects transistor performance, matching, and
  extraction
• Is the major deterministic source of device
  variability, e.g.,
• Gate length variation
• Line end pullback
• Widening/Thinning, etc.
• Complicates performance estimation/bin sort yield

Source Pack et al., SPIE 2003
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More Sources of Variability
Causes Vt Variations
From Borkar et al., GVLSI 2002 Grobman, DAC 2001
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Metallization Issues
Large topographical variation caused by soft pad
and mechanical properties
IsolatedTransistor
Dense Array
CMP,SOG
Contact Overetch causes leakage
RIE
Etc.
Source R. Pack, Cadence
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More Lithography Issues
Source Mentor Graphics, DAC 2004
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Complexity Defocus
Lens
Distance from lens
Image derived from R. Pack
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Impact of Defocus
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Complexity Aberration
From R. Pack
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Complexity Context Sensitivity
Source Pack et al., SPIE 2003
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Etc.

• Overall static variability is on the rise

From S. Nassif, ISPD 2004
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Impact of Static Variability
1.4
1.3
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Frequency 30 Leakage Power 5-10X
1.2
130nm
Normalized Frequency
1000 samples
1.1
1.0
0.9
1
2
3
4
5
Normalized Leakage (
Isb
)
From Borkar et al., GVLSI 2002
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Dynamic Variability

• Voltage
• Activity change
• Power deliveryRLC
• Dynamicns to 10-100 uSec
• Within die
• Temperature
• Change in activity and ambient
• Dynamic 100s of uSec to mSec
• Within die

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Temperature Profile Example

• Varies spatially and with time (switching
  activity)

From C. Visweswariah, IBM
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Impact of Temperature Variability
S
S
1
1
2
2
3
3
4
4
5
5
6
6
7
7
From S.A. Bota, et al., ITC2004
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A Chip at Work
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Impact of IR Drop and Power Supply Noise

• Normalized circuit delay (simulated)

w/ supply noise
w/ IR drop
w/o supply noise
From Y.M. Jiang and K.T. Cheng, UCSB
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What Does That Mean?

• Yield limiters may buried inside the product
  design
• Very context-sensitive and design specific
• Non-visual and not represented in test vehicles

WorstCaseSpec
StatisticalSpec
EDAModel
Probability
Parameter
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The New Role of Test

• Test may be the first real opportunity to uncover
  the statistical impact of new catastrophic and
  parametric defect sources
• Test can become a key tool for statistical design
  verification and design/yield learning

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Our Agenda for the Semester