FPGA

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FPGA
2
4. não faz nada
case idx is when 0gt ext_alt "00" rs when
1gt cs lt '1'ext_dlt cmd when 2gt cs lt
'0' when 3gt null end case
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library IEEE use IEEE.STD_LOGIC_1164.ALL use
IEEE.NUMERIC_STD.ALL entity lcd is port
( clk48 in std_logic rst in
std_logic ext_a out std_logic_vector(2
downto 0) ext_d out std_logic_vector(7
downto 0) ext_rw out std_logic cs_lcd
out std_logic csn_lcd out
std_logic ) end lcd --------------------------
--------------------------------------------------
----
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--------------------------------------------------
-------------- -- 2003 by Valery Sklyarov and
Iouliia Skliarova -- DETUA, IEETA, Aveiro
University, Portugal ----------------------------
------------------------------------ -- in this
example a part of VHDL code from Trenz electronic
was used -----------------------------------------
----------------------- -- Interaction with
HD44780U Dot Matrix LCD controller/driver -- LCD
2 lines x 16 characters --------------------------
-------------------------------------- library
IEEE use IEEE.STD_LOGIC_1164.ALL use
IEEE.NUMERIC_STD.ALL use IEEE.STD_LOGIC_UNSIGNED.
ALL entity Hitachi_lcd is port ( clk48
in std_logic -- clock 48 MHz rst
in std_logic -- reset ext_a out
std_logic_vector(2 downto 0) -- LCD
control ext_d out std_logic_vector(7 downto
0) -- LCD data ext_rw out std_logic
-- LCD read/write cs_lcd out std_logic
-- LCD chip select active high csn_lcd out
std_logic -- LCD data direction ) end
Hitachi_lcd
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--------------------------------------------------
------------------------------ architecture
Behavioral of Hitachi_lcd is signal clk
std_logic -- local clock signal div
unsigned (14 downto 0) -- local clock divider
signal reset std_logic -- lcd reset
sequence active signal cmd std_logic_vector (7
downto 0) -- data/command to lcd signal rs
std_logic -- register select bit for
lcd signal idx integer range 0 to 3 --
sequencer index for lcd timing signal cs
std_logic -- chip select for lcd signal cnt
unsigned (5 downto 0) -- character, command
counter constant line1 string(1 to 16) "LCD
operations " -- strings to display constant
line2 string(1 to 4) "DEMO" begin process(c
lk48, rst) -- local clock generator begin if
rst '1' then div lt (othersgt '0') elsif
rising_edge(clk48) then divlt div 1 end
if end process clklt div(div'left)
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process(clk, rst) -- LCD sub-clocks
sequencer begin if rst '1' then idx lt
0 elsif rising_edge(clk) then if idx 3 then
idxlt 0 else idxlt idx 1 end if end if end
process process(clk, rst) -- LCD local
control signals generator begin if rst '1'
then cs lt '0' ext_a lt (othersgt
'0') ext_d lt (othersgt '0') elsif
rising_edge(clk) then case idx is when
0gt ext_alt "00" rs -- set register
address when 1gt cs lt '1'ext_dlt cmd
-- write data, activate chip select when 2gt
cs lt '0' -- deactivate chip select
when 3gt null -- data hold
time end case end if end
process ext_rwlt '0' -- always write to
LCD cs_lcd lt cs -- chip select for
LCD csn_lcdlt '0' -- always write to LCD
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process(clk, rst) begin if rst '1'
then cmd lt x"02" -- clear DDRAM counter,
switch off shift rs lt '1' reset lt '1' --
activate LCD initialization from the
beginning cnt lt (others gt '0') elsif
rising_edge(clk) then if idx 2 then cnt lt
cnt 1 end if if (reset '0') then --
normal functionality after initialization ca
se cnt is when "000000" gt cmd lt x"80"
rs lt '0'-- DDRAM address to the beginning of
the first line when "000001" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(1
)), 8)) rs lt '1' when "000010" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(2
)), 8)) rs lt '1' when "000011" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(3
)), 8)) rs lt '1' when "000100" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(4
)), 8)) rs lt '1' when "000101" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(5
)), 8)) rs lt '1' when "000110" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(6
)), 8)) rs lt '1' when "000111" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(7
)), 8)) rs lt '1' when "001000" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(8
)), 8)) rs lt '1' when "001001" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(9
)), 8)) rs lt '1' when "001010" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(1
0)), 8)) rs lt '1' when "001011" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(1
1)), 8)) rs lt '1' when "001100" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(1
2)), 8)) rs lt '1' when "001101" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(1
3)), 8)) rs lt '1' when "001110" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line1(1
4)), 8)) rs lt '1'
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when "001111" gt cmd lt std_logic_vector(to_un
signed(character'pos(line1(15)), 8)) rs lt '1'
when "010000" gt cmd lt std_logic_vector(to_uns
igned(character'pos(line1(16)), 8)) rs lt '1'
when "010001" gt cmd lt x"C0" rs lt '0'--
DDRAM address to the beginning of the second
line when "010-1-""0101--" gt cmd lt x"20"
rs lt '1' when "011000" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line2(1
)), 8)) rs lt '1' when "011001" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line2(2
)), 8)) rs lt '1' when "011010" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line2(3
)), 8)) rs lt '1' when "011011" gt cmd lt
std_logic_vector(to_unsigned(character'pos(line2(4
)), 8)) rs lt '1' when "0111--""10000-" gt
cmd lt x"20" rs lt '1' when "100010" gt
cmd lt x"80" rs lt '0' when others gt
cmd lt x"80" rs lt '0'--cnt lt "000000" end
case else -- initialization of LCD from the
beginning case cnt is -- delay such as from
"000000" to "001000" is important
-- for satisfying LCD timing requirements
when "000000" gt cmd lt x"38" rs lt '0' --
(x"20" Function Set)(x"10" 8-bit data) --
(x"08" two lines) when "001000" gt cmd
lt x"0C" rs lt '0' -- (x"08" display
control)(x"04" display on) -- (x"00"
cursor off - our case x"02" cursor on) when
"010000" gt cmd lt x"06" rs lt '0' -- (x"04"
entry mode set)(x"02" increment on) when
"011000" gt cmd lt x"01" rs lt '0' -- (x"01"
clear display and DDRAM counter) when
"100000" gt reset lt '0' cnt lt "000000" --
initialization is finished when others gt
null end case end if end if end
process end Behavioral
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constant line1 string(1 to 16) "LCD operations
" -- strings to display
VHDL Reserved Word constant Purpose A class of
data object. Constants can hold a single value of
a given type. If the value is not specified, the
constant is a deferred constant, and can appear
inside a package declaration only. Syntax consta
nt_declaration constant identifier_list
subtype_indication expression Example cons
tant alpha character 'a' Example, deferred
constant constant no_of_outputs integer
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VHDL Reserved Word null Purpose Sequential
statement that causes no action to take
place execution continues with the next
statement. Syntax null_statement label
null Example if (sum gt 100) then p1 null
B1111 binary bit vector literal O353
octal bit vector literal XA5 hexadecimal
bit vector literal
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Scalar Types Enumerated Character (literals 128
characters of the ASCII character
set) Bit Boolean (literals true,
false) Severity_level (literals note, warning,
error, failure) Numeric Integer Physical Floating_
point
Signal attribute 'pos' indicates that unspecified
logic should be given the value of 0.
when "01111" gt lcdout lt std_logic_vector(to_uns
igned(character'pos(line2(1)), 8))
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