Advanced Topics in VHDL

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Advanced Topics in VHDL

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Title: Advanced Topics in VHDL

1
Lesson 3

Advanced Topics in VHDL
some of the slides are taken from
http//www.microlab.ch/courses/vlsi/vlsi21.pdf.

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Topics

Hierarchy, Abstraction, and Accuracy
Generics
Configuration
Subprograms, Packages and Libraries
Finite State Machines
I/O Files
Testbench

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Hierarchy, Abstraction, and Accuracy

Structural models simply describe
interconnections
Structural models do not describe any form of
behavior
Hierarchy expresses different levels of detail
Structural models are a way to manage large,
complex designs
Modern designs have several 10 millions of gates
Simulation time the more detailed a design is
described, the more events are generated and thus
the larger the simulation time will be needed.

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Generics
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More on Generics

Within a structural model there are two ways in
which the values of generic constants of lower
level components can be specified
in the component declaration
in the component instantiation
If both are specified, then the value provided by
the generic map() takes precedence.
If neither is specified, then the default value
defined in the model is used.

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Configuration

Structural models may employ different levels of
abstraction.
Each component in a structural model may be
described as a behavioral or a structural model.
Configuration allows stepwise refinement in a
design cycle.
Configuration represents resource binding.
Description-synthesis design method.

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Configuration Component Binding

Example of binding architectures A bit-serial
adder.
One of the different architectures must be bound
to the component C1 for simulation
Entity is not bound as interfaces do not change

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Configuration Default Binding Rules

To analyze different implementations, we simply
change the configuration, compile and simulate.
When newer component models become available we
bind the new architecture to the component
Default binding rules
If the entity name is the same as the component
name, then this entity is bound to the component.
if there are different architectures in the
working directory, the last compiled architecture
is bound to the entity

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Subprograms, Packages and Libraries

VHDL provides mechanisms for structuring
programs, reusing software modules, and otherwise
managing design complexity.
Packages contain definitions of procedures and
functions that can be shared across different
VHDL models.
Packages may contain user defined data types and
constants and can be placed in libraries.

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Overloaded AND Operator
type MVL4 is ('X','0','1','Z') type MVL4_TABLE
is array (MVL4, MVL4) of MVL4 function "and" (L,
R MVL4) return MVL4 is constant table_AND
MVL4_TABLE (('X', '0', 'X', 'X'),
('0', '0', '0', '0'), ('X', '0', '1',
'X'), ('X', '0', 'X', 'X')) begin
return table_AND(L, R) end "and"
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Features of Overloading

Values, operators, and subprograms can be
overloaded
How does the compiler differentiate between
overloaded and normal objects?
values? - type marks
operators and subprograms? - parameter and result
profiles

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Overloaded Type Conversion Function
function INTVAL(VAL MVL4_VECTOR) return INTEGER
is variable SUM INTEGER 0 begin for N
in VALLOW to VALHIGH loop assert
not(VAL(N) X or VAL(N) Z) report
INTVAL inputs not 0 or 1 severity
WARNING if VAL(N) 1 then SUM
SUM (2N) end if end loop
return SUM end INTVAL
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Continued
function INTVAL(VAL BIT_VECTOR) return INTEGER
is variable SUM INTEGER 0 begin for N
in VALLOW to VALHIGH loop if VAL(N) 1
then SUM SUM (2N) end if
end loop return SUM end INTVAL
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Overloaded In A Package
PACKAGE math IS FUCNTION (1, r BIT_VECTOR)
return INTEGER END math PACKAGE BODY math is
FUNCTION vector_to_int(S BIT_VECTOR) RETURN
INTEGER IS VARIABLE result INTEGER 0 ---
this function is local to VARIABLE prod
INTEGER 1 --- the package BEGIN FOR i IN
sRANGE LOOP IF s(i) 1 THEN
result result prod END IF prod
prod 2 END LOOP RETURN result END
vector_to_int
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Continued
FUNCTION (1, r BIT_VECTOR) RETURN INTEGER
IS BEGIN RETURN(vector_to_int(1)
vector_to_int(r)) END END math USE
WORK.math.ALL ENTITY adder IS PORT(a, b IN
BIT_VECTOR(0 TO 7) c IN INTEGER
dout OUT INTEGER) END adder ARCHITECTURE test
OF adder IS SIGNAL internal INTEGER BEGIN
internal lt a b --- which ? dout lt c
internal --- which ? END test
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Libraries
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Example Libraries and Packages
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Finite State Machines and VHDL

State Processes
State Coding
FSM Types
Medvedev
Moore
Mealy
Registered Output

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1. One "State" Process









FSM_FF process (CLK, RESET)begin    if RESET'1' then         STATE lt START      elsif CLK'event and CLK'1' then        case STATE is                when START   gt if XGO_MID then                                 STATE lt MIDDLE                               end if                 when MIDDLE gt if XGO_STOP then                                 STATE lt STOP                               end if                 when STOP    gt if XGO_START then                                 STATE lt START                               end if                 when others gt STATE lt START              end case     end if end process FSM_FF
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2. Two "State" Processes









FSM_FF process (CLK, RESET)    begin    if RESET'1' then         STATE lt START      elsif CLK'event and CLK'1' then         STATE lt NEXT_STATE      end ifend process FSM_FF FSM_LOGIC process ( STATE , X)begin     NEXT_STATE lt STATE     case STATE is           when START   gt if XGO_MID then                            NEXT_STATE lt MIDDLE                         end if            when MIDDLE gt ...           when others gt NEXT_STATE lt START          end case end process FSM_LOGIC
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3. How Many Processes?
Structure and Readability
Asynchronous combinatoric ? synchronous storing
elementsgt 2 processes
FSM states change with special input changesgt 1
process more comprehensible
Graphical FSM (without output equations)
resembles one state processgt 1 process
Simulation
Error detection easier with two state
processesgt 2 processes
Synthesis
2 state processes can lead to smaller generic net
listand therefore to better synthesis resultsgt
2 processes

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4. State Encoding


type STATE_TYPE is ( START, MIDDLE, STOP ) signal STATE STATE_TYPE State encoding responsiblefor safety of FSM
START      -gt " 00 "MIDDLE   -gt " 01 "STOP       -gt " 10 " Default encoding binary
START     -gt " 001 "MIDDLE   -gt " 010 "STOP       -gt " 100 " Speed optimized defaultencoding one hot
      if ld( of states) ? ENTIERld( of states) gt unsafe FSM!       if ld( of states) ? ENTIERld( of states) gt unsafe FSM!
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5. Extension of Case Statement



type STATE_TYPE is (START, MIDDLE, STOP) signal STATE  STATE_TYPE     case STATE is           when START     gt            when MIDDLE  gt            when STOP      gt             when others      gt     end case Adding the "when others" choice
     Not simulatablein RTL there exist no other values for STATE      Not necessarily safesome synthesis tools will ignore "when others" choice      Not simulatablein RTL there exist no other values for STATE      Not necessarily safesome synthesis tools will ignore "when others" choice
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6. Extension of Type Declaration


type STATE_TYPE is (START, MIDDLE, STOP, DUMMY) signal STATE  STATE_TYPE     case STATE is           when START     gt            when MIDDLE  gt            when STOP      gt             when DUMMY      gt     -- or when others    end case Adding dummy values Advantages Now simulatable Safe FSM after synthesis
     2(ENTIER ld(n)) -n dummy states(n20 gt 12 dummy states)      Changing to one hot coding gt unnecessary hardware(n20 gt 12 unnecessary FlipFlops)      2(ENTIER ld(n)) -n dummy states(n20 gt 12 dummy states)      Changing to one hot coding gt unnecessary hardware(n20 gt 12 unnecessary FlipFlops)
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7. Hand Coding


subtype STATE_TYPE is std_ulogic_vector (1 downto 0) signal STATE  STATE_TYPE constant START    STATE_TYPE  "01"constant MIDDLE  STATE_TYPE  "11"constant STOP      STATE_TYPE  "00"    case STATE is           when START     gt            when MIDDLE  gt            when STOP      gt            when others      gt     end case Defining constants Control of encoding Safe FSM Simulatable Portable design More effort
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8. FSM Medvedev
The output vector resembles the state
vector Y S

        Two Processes architecture RTL of MEDVEDEV is    ...begin     REG process (CLK, RESET)    begin        -- State Registers Inference    end process REG      CMB process (X, STATE)    begin       -- Next State Logic    end process CMB     Y lt S end RTL          One Process architecture RTL of MEDVEDEV is    ...begin     REG process (CLK, RESET)    begin        -- State Registers Inference with Logic Block    end process REG     Y lt S end RTL
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9. Medvedev Example


architecture RTL of MEDVEDEV_TEST is    signal STATE,NEXTSTATE  STATE_TYPE begin     REG process (CLK, RESET)    begin        if RESET1 then            STATE lt START         elsif CLKevent and CLK1 then            STATE lt NEXTSTATE         end if     end process REG     CMB process (A,B,STATE) begin        NEXT_STATE lt STATE        case STATE is            when START  gt if (A or B)0 then                            NEXTSTATE lt MIDDLE                         end if             when MIDDLE gt if (A and B)1 then                            NEXTSTATE lt STOP                          end if             when STOP    gt if (A xor B)1 then                            NEXTSTATE lt START                          end if             when others gt NEXTSTATE lt START         end case     end process CMB     -- concurrent signal assignments for output     (Y,Z) lt STATE end RTL
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10. Waveform Medvedev Example









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11. FSM Moore
The output vector is a function of the state
vector Y f(S)

       Three Processes architecture RTL of MOORE is    ...begin     REG -- Clocked Process     CMB -- Combinational Process    OUTPUT process (STATE)    begin        -- Output Logic    end process OUTPUT end RTL        Two Processes architecture RTL of MOORE is    ...begin     REG process (CLK, RESET)    begin        -- State Registers Inference with Next State Logic    end process REG     OUTPUT process (STATE)    begin        -- Output Logic    end process OUTPUT end RTL
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4.5.12 Moore Example


architecture RTL of MOORE_TEST is    signal STATE,NEXTSTATE STATE_TYPE begin    REG process (CLK, RESET) begin        if RESET1 then    STATE lt START         elsif CLKevent and CLK1 then            STATE lt NEXTSTATE         end if     end process REG     CMB process (A,B,STATE) begin        NEXT_STATE lt STATE        case STATE is          when START gt if (A or B)0 then                            NEXTSTATE lt MIDDLE                          end if           when MIDDLE gt if (A and B)1 then                            NEXTSTATE lt STOP                          end if           when STOP    gt if (A xor B)1 then                            NEXTSTATE lt START                          end if           when others gt NEXTSTATE lt START         end case      end process CMB     -- concurrent signal assignments for output    Y lt ,1 when STATEMIDDLE else ,0     Z lt ,1 when STATEMIDDLE                or STATESTOP else ,0 end RTL
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13. Waveform Moore Example









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14. FSM Mealy
The output vector is a function of the state
vectorand the input vector Y f(X,S)

       Three Processes architecture RTL of MEALY is    ...begin    REG -- Clocked Process    CMB -- Combinational Process    OUTPUT process (STATE, X)    begin        -- Output Logic    end process OUTPUT end RTL        Two Processes architecture RTL of MEALY is    ...begin    MED process (CLK, RESET)    begin        -- State Registers Inference with Next State Logic    end process MED     OUTPUT process (STATE, X)    begin        -- Output Logic    end process OUTPUT end RTL
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15. Mealy Example


architecture RTL of MEALY_TEST is    signal STATE,NEXTSTATE STATE_TYPE begin    REG    -- clocked STATE process    CMB    -- Like Medvedev and Moore Examples    OUTPUT process (STATE, A, B)    begin        case STATE is           when START   gt                                          Y lt 0                                           Z lt A and B            when MIDLLE  gt                                          Y lt A nor B                                           Z lt '1'            when STOP     gt                                          Y lt A nand B                                           Z lt A or B            when others  gt                                          Y lt 0                                           Z lt '0'         end case    end process OUTPUTend RTL
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16. Waveform Mealy Example
(Y,Z) changes with input gt Mealy machine
Note the "spikes" of Y and Z in the waveform
FSM has to be modeled carefully in order to avoid
spikes in normal operation.

17. Modelling Aspects
Medvedev is too inflexible
Moore is preferred because of safe operation
Mealy more flexible, but danger of
Spikes
Unnecessary long paths (maximum clock period)
Combinational feed back loops

1. 8 Registered Output
Avoiding long paths and uncertain timing
With one additional clock period
Without additional clock period (Mealy)

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19. Registered Output Example (1)


architecture RTL of REG_TEST is    signal Y_I , Z_I std_ulogic     signal STATE,NEXTSTATE STATE_TYPE begin    REG    -- clocked STATE process    CMB    -- Like other Examples    OUTPUT process (STATE, A, B)    begin        case STATE is           when START   gt                                          Y_Ilt 0                                           Z_Ilt A and B                 end process OUTPUT    -- clocked output process    OUTPUT_REG process(CLK)    begin        if CLK'event and CLK'1' then         Y lt Y_I          Z lt Z_I         end if     end process OUTPUT_REG end RTL
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20. Waveform Registered Output Example (1)
One clock period delay between STATE and output
changes.
Input changes with clock edge result in an output
change.(Danger of unmeant values )

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21. Registered Output Example (2)


architecture RTL of REG_TEST2 is    signal Y_I , Z_I std_ulogic     signal STATE,NEXTSTATE STATE_TYPE begin    REG    -- clocked STATE process    CMB    -- Like other Examples    OUTPUT process ( NEXTSTATE , A, B)    begin        case NEXTSTATE is           when START   gt                                          Y_Ilt 0                                           Z_Ilt A and B                 end process OUTPUT    OUTPUT_REG process(CLK)    begin        if CLK'event and CLK'1' then         Y lt Y_I          Z lt Z_I         end if     end process OUTPUT_REG end RTL
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2. 2 Waveform Registered Output Example (2)








     No delay between STATE and output
changes.

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