Instruction Set Architecture

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Instruction Set Architecture

• ISA formal definition of h/w meets s/w
• ISA formal specification of compiler meets
  microarchitecture
• All HLLs resolve to an ISA after a compile
• ISA memory model register model
  data model instruction
  model

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ISA is a Contract
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Memory Model

• First item is typically the stack handling
• How will a procedure call another?
• How to handle parameters and return values?
• A second item is alignment
• Byte versus word versus other alignment
• Determines boundaries for data
• Boundaries defined in multiples of bytes
• Also little-endian or big-endian

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Register Model

• How many and for what purposes?
• Special- versus general-purpose
• General purpose often hold calculation results
• Internal registers like SP, PC, etc.
• An important one the flags/status register
• Holds bits for Z, N, overflow, etc.
• Holds bits for mode of processor

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Data Model

• Need a plan to represent basic types
• Choose instructions based on types, e.g.
• Add instructions for 32-bit integers
• Add instructions for 64-bit integers
• Add instructions for 32-bit real numbers
• Add instructions for 64-bit real numbers
• Real issue what ops does the CPU support?

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Instruction Model

• Main pieces opcodes and operands
• Operands must be addressable
• Some possible modes for addressing
• immediate (value directly in instruction)
• direct (address directly in instruction)
• register (instruction names register w/ value)
• register indirect (register has address)
• based-indexed (offsets from register address)

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Pentium Instructions

• Compatibility is king
• Know your ancestors
• First major chip ancestor was 8086 8088
• Then came 286 and 32-bit 386
• Next came 486 and variations of Pentium
• All share a common subset of instructions
• Typically called the IA-32 architecture
• Instructions added for graphics, streaming data

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IA-32 Registers
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Some IA-32 Registers

• ESP is stack pointer (stacks top address)
• EBP is frame pointer
• active frames start/bottom address
• EIP is program counter
• Next instructions address
• EFLAGS is flags/status register
• EAX versus AX versus AH versus AL

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UltraSPARC

• SPARC introduced in 1987
• An early RISC machine and quite a scandal!
• Big endian (Pentium is little endian)
• Can emulate IA-32 (including little endian)
• Tons of registers 32 per window
• Called a load/store architecture

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UltraSPARC Register Windows
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Some UltraSPARC Registers

• 7 for global variables
• 1 for stack pointer
• 1 for current stack frame
• 1 for return address for current procedure
• 8 for local variables
• 6 for outgoing parameters
• 6 for incoming parameters