Introduction of SystemC Workshop

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Introduction of SystemC Workshop

• Media IC System Lab

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Outline

• Introduction of Todays Workshop
• System Level Design with ESL
• SystemC Tutorial
• What Is Coware ConvergenSC

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Introduction

• In SoC era, ESL (Electronic System Level)
  methodology is inevitable.
• Top-down vs. bottom-up
• System vs. module considerations

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SoC Design in The Future
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Fragmentation is the Root CauseLimits speed and
efficiency within projects
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Why ESL Methodology?

• Unifies all the different processes and stages
• Unifies from system design to system design-in

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Optimization Steps Towards Best fit

• Exploit regularity/parallelism in data flow/data
  storage
• Exploit regularity/parallelism in operation
• Optimized control of computations

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Its time to move up, yet again!
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SystemC Tutorial
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Layers of Hardware Design
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Scope of Layers

• No notion of time (processes and data transfers)
• Notion of time (processes and data transfers)
• Cycle accuracy, signal accuracy

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Purpose of Layers
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What language?

• Problem very different levels of abstraction
• Modeling language to use?
• High-level Java, Visual Basic, C
• Low-level HDLs (VHDL, Verilog)
• Huge modeling gap
• Need to translate models

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Design Overhead
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Why not just C?

• Concurrency support is missing (HW is inherently
  parallel)
• No notion of time (clock, delays)
• Communication model is very different from actual
  HW model (signals)
• Weak/complex reactivity to events
• Missing data types (logic values, bit vectors,
  fixed point math)

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SystemC Paradigm
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How can this be achieved?

• C extensions!
• New library (libsystemc.a) providing additional
  functionality
• Building upon C features (inheritance!) and
  data types to better express HW behavior
• SystemC HW-modeling code is actually C code
  and can be freely mixed with plain C

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SystemC Infrastructure
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SystemC Advantages

• Unified language across all stages of platform
  design (easier tool interoperability, designer
  training)\
• Unified language across HW and SW development
  (promoting co-design)
• Allows faster simulation/refinement/reworking of
  modules
• Builds upon one of the most widespread
  programming languages (many tools, programmers)
• Lightweight

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SystemC Toolchain
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SystemC Features

• Concurrency support modules
• Notion of time clocks, custom wait() calls
• Communication model signals, protocols,
  handshakes
• Reactivity to events support for events,
  sensitivity list, watching() construct
• Data types logic values, bit vectors, fixed
  point
• C /SystemC results in a suitable platform!

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ConvergenSC Overview

• The Product Family
• Tool Components
• Usage Examples
• Benefits

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CoWare SystemCComplete ESL to RTL Flow
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Vision Product Flow
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The ConvergenSC product family is a suite of
tools for system architecture and design
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The ConvergenSC product family consists of
System Verifier
System Designer
Advanced System Designer
Simulation and Debugging
Analysis
Platform Assembly and Configuration
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System Verifier provides the simulation and
debugging environment
Command Line Interface
Integrated Development Environment
Stack and control
Design Browser
Outline
Source Code
Input and Output
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System Designer adds analysis capabilities
Hardware
Memory
Software
Bus
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The SV / SD components consist of a SystemC
compiler, a command interpreter, a debugger and
the simulation engine
2. The command interpreter shell
3. An enhanced debugger
1. The SystemC Compiler
Source code.h .cpp
Optimize mode
Lenient mode
PseudoTTY interface
scopt
SystemC optimizer
TCL commands
SCC SystemC Compiler
4. Simulation engine
cxx
Analysis Views
Backend compiler (g)
Simulation Engine
Post Proc
db
ISS
Analysis
ISS Debugger
HDL CoSim
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Advanced System Designer is for architecture
optimization and system integration
Import of SystemC and HDL Blocks
HW/SW Partitioning and Interface Synthesis
IP Reuse based on XML meta-data
Block Diagram Editor
Export of SystemC and HDL Blocks
Scripting Interface
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ASD components consist of Platform Creator, XML
libraries, and the transactional bus simulator
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1 Use the ConvergenSC tools to create bus models
Platform Creator
Users tasks - Create bus topology - Configure
memory map - Set parameters - Perform error
checking - Export Hardware
Bus Library Handler automatically generates -
address decoders - muxes - arbiters - bridges
User models
BusLibrary Handler
Bus Library
IP Library
User writes sc_main and instantiates - Bus
Architecture model - core model(s) - all user
hardware models
sc_main
Bus Model.cpp .h .maf
SV/SD
Simulate
db
Post proc
Generate Analysis Views
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A System Bus is not just a collection of wires,
but contains structure and behavior

• Creating a bus model that has
• High speed simulation
• Cycle-accurate behavior
• Complex topology
• Support for HDL models
• is a difficult and time consuming task to do by
  handso

Which AMBA architecture for a JPEG platform is
best?
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The Bus Library provides components for bus
construction
Platform Creator

• Bus Assembly Toolset
• For creating fast cycle-accurate busses
• Explore different architectures graphically
• Automatic protocol correctness
• Pre-instrumented Analysis
• Immediately use bus, s/w and memory analysis
  tools to justify design decisions

BusLibrary Handler
Bus Library
IP Library
sc_main
Bus Model.cpp .h .maf
Iteratively measure and modify for optimum
performance

• and
• The benefits of TLM Bus Models

SV/SD
Simulate
Generate Analysis Views
db
Post proc
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Accuracy and speed for Transaction Level Modeling
are accomplished by these basic concepts
Event timing can trigger actions.
Bus Model
Initiator
Target
addressEvent()
dataEvent()
Address
Data
sendAddress()
sendData()
Initiator and Target use an API to communicate
via transfers.
Processes are only evaluated when there is a
relevant event.
Bus Model keeps track of timing.
AddressTransfer
ReadDataTransfer
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2 Use the ConvergenSC tools to build
platform-based designs
User models
Platform Creator
Users tasks - Create system design -
Configure memory map - Set parameters - Perform
error checking - Export Hardware
BusLibrary Handler
Bus Library
IP Library
Bus Model
Bus Library Handler automatically generates -
address decoders - muxes - arbiters - bridges
Platform Model.cpp .h .maf
User - Builds simulation - Configures
analysis
SV/SD
Simulate
db
Post proc
Generate Analysis Views
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3 Use the ConvergenSC tools to perform
hardware-software (top-down) design
SystemSpec
Platform Creator
Users tasks - Load platform or PSP -
Import UT system spec - Block partitioning -
HW/SW scenario selection - Configure memory
map - Set parameters - Perform error
checking - Export System
BusLibrary Handler
SW Systems.cpp .h
Bus Library
IP Library
Bus Model
Bus Library Handler automatically generates -
address decoders - muxes - arbiters - bridges
Compile
User - Compiles SW system - Builds
simulation - Configures analysis
HW Systems.cpp .h .maf
SV/SD
Simulate
db
Post proc
Generate Analysis Views
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The ConvergenSC product family provides

• Simulation
• - Fully compliant SystemC simulator
• - Optimizes design for high speed execution
• - TCL scripting language for simulation control
• - SystemC aware debugger
• TLM Modeling
• - High speed, cycle accurate bus architecture
  models
• Analysis
• - Waveforms event tracing
• - Performance statistics
• - Profiling coverage

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• HDL Co-Simulation
• System Level Design
• Easy assembly configuration of bus topologies
• Block diagram editor
• Platform development
• HW/SW partitioning and Interface Synthesis
• Export of SystemC and HDL blocks

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Conclusion
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