Lecture 1 Introduction to VLSI Design

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Lecture 1Introduction to VLSI Design

• Pradondet Nilagupta
• pom_at_ku.ac.th
• Department of Computer Engineering
• Kasetsart University

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Acknowledgement

• This lecture note has been summarized from
  lecture note on Introduction to VLSI Design, VLSI
  Circuit Design all over the world. I cant
  remember where those slide come from. However,
  Id like to thank all professors who create such
  a good work on those lecture notes. Without those
  lectures, this slide cant be finished.

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Todays Topics

• Course overview
• Objectives
• Roadmap for the Semester
• Administrative Details
• VLSI Overview
• Transistor Structure
• Static CMOS Logic
• Design Methods Design Styles
• VLSI Trends

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Course Objectives (1/3)

• Students should be able to
• VLSI Circuit Analysis
• Understand MOS transistor operation, design eqns.
• Understand parasitics perform simple
  calculations
• Understand static dynamic CMOS logic
• Estimate delay of CMOS gates, networks, long
  wires
• Estimate power consumption
• Understand design and operation of latches
  flip/flops

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Course Objectives (2/3)

• CMOS Processing and Layout
• Understand the VLSI manufacturing process.
• Have an appreciation of current trends in VLSI
  manufacturing.
• Understand layout design rules.
• Design and analyze layouts for simple digital
  CMOS circuits
• Design and analyze hierarchical circuit layouts.
• Understand ASIC Layout styles.

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Course Objectives (3/3)

• VLSI System Design
• Understand register-transfer level design.
• Design simple combinational and sequential logic
  circuits using using a Hardware Description
  Language (HDL).
• Design small to medium circuits consisting of
  multiple components such as a controller and
  datapath using a HDL.
• Understand the design flows used in industrial IC
  design.
• Design a small standard-cell chip in its entirety
  using a variety of CAD tools and check it for
  correct operation.

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Roadmap for the term major topics

• VLSI Overview
• CMOS Processing Fabrication
• Components Transistors, Wires, Parasitics
• Design Rules Layout
• Combinational Circuit Design Layout
• Sequential Circuit Design Layout
• Standard-Cell Design with CAD Tools Verilog
• Mixed Signal Concerns D/A, A/D Conversion
• Design Project Complete Chip

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VLSI Overview

• Why Make IC
• IC Evolution
• Common technologies
• CMOS Transistors Logic Gates
• Structure
• Switch-Level Transistor Model
• Basic gates
• The VLSI Design Process
• Levels of Abstraction
• Design steps
• Design styles
• VLSI Trends

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Why Make ICs

• Integration improves
• size
• speed
• power
• Integration reduce manufacturing costs
• (almost) no manual assembly

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IC Evolution (1/3)

• SSI Small Scale Integration (early 1970s)
• contained 1 10 logic gates
• MSI Medium Scale Integration
• logic functions, counters
• LSI Large Scale Integration
• first microprocessors on the chip
• VLSI Very Large Scale Integration
• now offers 64-bit microprocessors, complete with
  cache memory (L1 and often L2), floating-point
  arithmetic unit(s), etc.

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IC Evolution (2/3)

• Bipolar technology
• TTL (transistor-transistor logic)
• ECL (emitter-coupled logic)
• MOS (Metal-oxide-silicon)
• although invented before bipolar transistor, was
  initially difficult to manufacture
• nMOS (n-channel MOS) technology developed in
  1970s required fewer masking steps, was denser,
  and consumed less power than equivalent bipolar
  ICs gt an MOS IC was cheaper than a bipolar IC
  and led to investment and growth of the MOS IC
  market.

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IC Evolution (3/3)

• aluminum gates for replaced by polysilicon by
  early 1980
• CMOS (Complementary MOS) n-channel and p-channel
  MOS transistors gt lower power consumption,
  simplified fabrication process
• Bi-CMOS - hybrid Bipolar, CMOS (for high speed)
• GaAs - Gallium Arsenide (for high speed)
• Si-Ge - Silicon Germanium (for RF)

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(No Transcript)
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VLSI Technology - CMOS Transistors
2002 L130nm 2003 L90nm 2005 L65nm?
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Transistor Switch Model

• NFET or n transistor
• on when gate H
• "good" switch for logic L
• "poor" switch for logic H
• "pull-down" device
• PFET or p transistor
• on when gate L
• "good" switch for logic H
• "poor" switch for logic L
• "pull-up" device

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CMOS Logic Design

• Complementary transistor networks
• Pullup p transistors
• Pulldown - n transistors

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CMOS Inverter Operation
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CMOS Logic Example - Whats This?
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VLSI Levels of Abstraction
Specification (what the chip does, inputs/outputs)
Architecture major resources, connections
Register-Transfer logic blocks, FSMs, connections
Logic gates, flip-flops, latches, connections
Circuit transistors, parasitics, connections
Layout mask layers, polygons
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The VLSI Design Process

• Move from higher to lower levels of abstraction
• Use CAD tools to automate parts of the process
• Use hierarchy to manage complexity
• Different design styles trade off
• Design time
• Non-recurring engineering (NRE) cost
• Unit cost
• Performance
• Power Consumption

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VLSI Design Tradeoffs (1/2)

• Non-Recurring Engineering (NRE) Costs
• Design Costs
• Mask Tooling costs
• Unit Cost - related to chip size
• Amount of logic
• Current technology
• Performance
• Clock speed
• Implementation

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VLSI Design Tradeoffs (2/2)

• Power consumption - a relatively new concern
• Power supply voltage
• Clock speed

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VLSI Design Styles

• Full Custom
• Application-Specific Integrated Circuit (ASIC)
• Programmable Logic (PLD, FPGA)
• System-on-a-Chip

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Full Custom Design

• Each circuit element carefully handcrafted
• Huge design effort
• High Design NRE Costs / Low Unit Cost
• High Performance
• Typically used for high-volume applications

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Application-Specific Integrated Circuit (ASIC)

• Constrained design using pre-designed (and
  sometimes pre-manufactured) components
• Also called semi-custom design
• CAD tools greatly reduce design effort
• Low Design Cost / High NRE Cost / Med. Unit Cost
• Medium Performance

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Programmable Logic (PLDs, FPGAs)

• Pre-manufactured components with programmable
  interconnect
• CAD tools greatly reduce design effort
• Low Design Cost / Low NRE Cost / High Unit Cost
• Lower Performance

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System-on-a-chip (SOC)

• Idea combine several large blocks
• Predesigned custom cores (e.g., microcontroller)
  - intellectual property (IP)
• ASIC logic for special-purpose hardware
• Programmable Logic (PLD, FPGA)
• Analog
• Open issues
• Keeping design cost low
• Verifying correctness of design

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Perspective on Design Styles

• Few engineers will design custom chips
• Some engineers will design ASICs SOCs
• Many engineers will design FPGA systems

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VLSI Trends Moores Law

• In 1965, Gordon Moore predicted that transistors
  would continue to shrink, allowing
• Doubled transistor density every 18-24 months
• Doubled performance every 18-24 months
• History has proven Moore right
• But, is the end is in sight?
• Physical limitations
• Economic limitations

Im smiling because I was right!
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Microprocessor Trends (Intel)
Source http//www.intel.com/pressroom/kits/quickr
effam.htm
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Microprocessor Trends
Sources http//www.intel.com/pressroom/kits/quick
reffam.htm, www.geek.com
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Microprocessor Trends (Log Scale)
Sources http//www.intel.com/pressroom/kits/quick
reffam.htm, www.geek.com
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DRAM Memory Trends (Log Scale)
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Processor Performance Trends
Source Hennesy Patterson Computer
Architecture A Quantitative Approach, 3rd Ed.,
Morgan-Kaufmann, 2002.
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Trends in VLSI

• Transistor
• Smaller, faster, use less power
• Interconnect
• Less resistive, faster, longer (denser design)
• Yield
• Smaller die size, higher yield

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Summary - Technology Trends

• Processor
• Logic capacity increases 30 per year
• Clock frequency increases 20 per year
• Cost per function decreases 20 per year
• Memory
• DRAM capacity increases 60 per year (4x
  every 3 years)
• Speed increases 10 per year
• Cost per bit decreases 25 per year

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Technology Directions SIA Roadmap
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Scaling

• The process of shrinking the layout in which
  every dimension is reduced by a factor is called
  Scaling.
• Transistors become smaller, less resistive,
  faster, conducting more electricity and using
  less power.
• Designs have smaller die sizes, higher yield and
  increased performance.

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Can Scaling Continue?

• Scaling work well in the past
• In order to keep scaling work in the future, many
  technical problems need to be solved.

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Can Scaling Continue?

• Some characteristics of the transistors do not
  scale uniformly, e.g., delay, leakage current,
  threshold voltage, etc.
• Mismatch in the scaling of transistors and
  interconnects. Interconnect delay has increased
  from 5-10 of the overall delay to 50-70.

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Roadmap

• International Technology Roadmap for
  Semi-conductors (ITRS)
• Projection of future technology requirements for
  the next 15 years.

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These trends have brought many changes and new
challenges to circuit design.
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Complicated Design

• Too many transistors and no way to handle them
  manually.
• Solutions
• CAD
• Hierarchical design
• Design re-use

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Power and Noise

• Huge power consumption and heat dissipation
  becomes a problem
• Noise and cross talk.
• Solutions
• Better physical design

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Interconnect Area

• Too many interconnects
• Solutions
• More interconnect layers (made possible by
  Chemical-Mechanical Polishing)
• CAD tools for 3-D routing

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Interconnect Delay

• Interconnect delay becomes a dominating factor in
  circuit performance
• Solutions
• Use copper wire
• Interconnect optimization in physical design,
  e.g., wire sizing, buffer insertion, buffer
  sizing.

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Interconnect Delay
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Gallery - Early Processors
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Intel 4004

• Introduction date November 15, 1971
• Clock speed 108 KHz
• Number of transistors 2,300 (10 microns)
• Bus width 4 bits
• Addressable memory 640 bytes
• Typical use calculator, first microcomputer
  chip, arithmetic manipulation

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Gallery - Current Processors
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Gallery - Current Processors
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Pentium 4

• 0.18-micron process technology (2, 1.9, 1.8,
  1.7, 1.6, 1.5, and 1.4 GHz)
• Introduction date August 27, 2001 (2, 1.9 GHz)
  ... November 20, 2000 (1.5, 1.4 GHz)
• Level Two cache 256 KB Advanced Transfer Cache
  (Integrated)
• System Bus Speed 400 MHz
• SSE2 SIMD Extensions
• Transistors 42 Million
• Typical Use Desktops and entry-level
  workstations
• 0.13-micron process technology (2.53, 2.2, 2
  GHz)
• Introduction date January 7, 2002
• Level Two cache 512 KB Advanced
• Transistors 55 Million

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Intels McKinley

• Introduction date Mid 2002
• Caches 32KB L1, 256 KB L2, 3MB L3 (on-chip)
• Clock 1GHz
• Transistors 221 Million
• Area 464mm2
• Typical Use High-end servers
• Future versions5GHz, 0.13-micron technology

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Gallery - Current FPGA
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Gallery - Graphics Processor
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What were going to do

• Chip design MOSIS tiny chip

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What were going to do

• Fabricated MOSIS Tiny Chip

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Die Photo - 2001 Design Project
Chip Design by Ed Thomas Photo courtesy Ron
Feiller, Agere