SNAP Electrical Design Estimates

1
SNAPElectrical Design Estimates
Super Nova/Acceleration Probe

• November 16, 2001
• C. Paul Earle

2
SNAP Functional Block Diagram
Thermal Control Monitoring
Shutter Control
Bright Object Detector
FPA
S/C CDH
FPE
1553 I/F
ICE
Scene
Readout Control Logic
Instrument Control Electronics
Science Data I/F
Mass Storage (S/C)
Data Buffering
Detectors
Filters
CDS
A/D
Shutter
Door
DC-DC Converter
Spectrograph
A/D
Focus Control
S/C Power
Door open / close
Figure 1.
3
Science Data Rate
FPA Size 144 CCDs _at_ 1.6Kx1.6K each 368.6
Mpix 44 HgCdTe _at_ 2Kx2K each 176
Mpix Spectrograph 1Kx1K 1Mpix Average Data
Rate gt 545 Mpix for each 200Sec exposure gt
Data rate (avg) (545Mpix/220Sec) 2.5Mpix/s
40 Mbps _at_16-bits/pix 20 Mbps
(with 21 loss-less compression)
220Sec
200Sec integration
20Ssec readout
4
Focal Plane Electronics
CCD Readout ASIC (3 x 3) each

• 4 A/Ds
• 4 CDS chips (Correlated Double Sampling)
• Bias Power Generation
• Sequencer Clock Drivers
• 188 Readout ASICs
• 10 boards (12 x 12)
• 18 ASICs each, 9 ASICs per side
• 2 boxes (13.5x13.5x6) each 9lbs each
• Total Power 156Watt (peak), 22 Watt (avg.)

5
Thermal Control
Requirements - 70 zones, controlled within 0.5
deg. C of set point - 1 Heater and 1 Temperature
Sensor per zone - Each CCD controlled within 0.1
deg. C of set point - Unregulated Heater Power
(120Watts)
V
V
V
Heater
Sensor (AD590)
i (T)
(1 of 258)
Current TLM
Figure 2.
6
CCD Temperatures
Housekeeping Data
(1 of 11)
A/D Conv. AD 1672
H/K FIFO
Mux 16-ch AD506
V-
To Memory

CCD temps (188)
-
V-
Zone Temperatures Other Telemetry points
(1 of 5)
Mux 16-ch AD506
A/D Conv. AD 1672
H/K FIFO
Power Temp ...
. . .
To Memory
Figure 3.
7
Readout Data Buffering
(1 of 188)
(1 of 188)
FIFO Buffer
Digital MUX (41)
CCD I/F
To Storage
4
1
Capture Control Logic FPGA (1 of 1)
Processor Card I/F
FPE I/F
Figure 4.
8
Mechanism Control
(Door Control Electronics)
Figure 6.
9
Processor Memory Board
Startup ROM
xfmr
xcvr
1553 I/F
CPU UTMC 69R000
xfmr
xcvr
xfmr
1553 I/F
xfmr
RAM (Data Processing)
EEPROM Memory (Data Processing)
Ethernet I/F
S/W Dev.
Figure 5.
10
Power Distribution
DC/DC Converters
15 V
28 VDC
5 V
Current Sense

-
Voltage Sense

-
Figure 7.
11
Board Estimates
10 in
Thermal Control (4W)
Data Buffer (3W)
Mech Control (6W)
Thermal Control (4W)
Data Buffer (3W)
Housekeeping (16W)
Thermal Control (4W)
Data Buffer (3W)
Processor (4W)
9 in
FPE Power (9.4W)
Main Power (20W)
Figure 8.
12
Main Electronics Box Summary
10 in
Estimated Mass 44 lbs Estimated Power 76
Watts (avg.) Estimated Size (19 x 11 x 10) in.
11 in
19 in
Figure 9.