Computer Architecture

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Computer Architecture

• Lecture 18
• Superscalar Processor and High Performance
  Computing

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Static Superscalar Pipeline

• Fetch 64-bits/clock cycle Int on left, FP on
  right
• Can only issue 2nd instruction if 1st
  instruction issues
• More ports for FP registers to do FP load FP
  op in a pair
• Type Pipe Stages
• Int. instruction IF ID EX MEM WB
• FP instruction IF ID EX MEM WB
• Int. instruction IF ID EX MEM WB
• FP instruction IF ID EX MEM WB
• Int. instruction IF ID EX MEM WB
• FP instruction IF ID EX MEM WB
• 1 cycle load delay can cause delay up to 3
  instructions in Superscalar - instruction in
  right half cant use it, nor instructions in next
  slot

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Dynamic Super Scalar pipeline in operation
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Example 1

• Loop L.D F0,0(R1) F0array element
• ADD.D F4,F0,F2
• S.D F4,0(R1) store result
• ADDIU R1,R1,-8 8 bytes (per DW)
• BNE R1,R2,LOOP branch R1!R2

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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Dual issue, 1 Integer Unit
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Separate MEM and INT
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Dual issue, 2 Integer Unit
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Speculative Execution

• Need to overcome
• Branch Hazards
• Precise Exception

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Speculative Pipeline
Read Reg
ROB
CDB
ISSUE/ Rename to RS
FP
Write Reg
Check for RS
Check for RAW
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The Hardware Reorder Buffer
IM

• If inst write results in program order,
  reg/memory always get the correct values
• Reorder buffer (ROB) reorder out-of-order inst
  to program order at the time of writing
  reg/memory (commit)
• If some inst goes wrong, handle it at the time of
  commit just flush inst afterwards
• Inst cannot write reg/memory immediately after
  execution, so ROB also buffer the results
• No such a place in Tomasulo original

Fetch Unit
Reorder Buffer
Decode
Rename
Regfile
RS
RS
L-buf
S-buf
DM
FU1
FU2
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Speculative Tomasulo Algorithm
Issue get instruction from FP Op
Queue Condition a free RS at the required
FU Actions (1) decode the instruction (2)
allocate a RS and ROB entry (3) do source
register renaming (4) do dest register renaming
(5) read register file (6) dispatch the decoded
and renamed instruction to the RS and
ROB Execution operate on operands
(EX) Condition At a given FU, At lease one
instruction is ready Action select a ready
instruction and send it to the FU Write result
finish execution (WB) Condition At a given FU,
some instruction finishes FU execution Actions
(1) FU writes to CDB, broadcast to all RSs and to
the ROB (2) FU broadcast tag (ROB index) to all
RS (3) de-allocate the RS. Note no register
status update at this time
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Speculative Tomasulo Algorithm

• Commitupdate register with reorder result
• Condition ROB is not empty and ROB head inst has
  finished execution
• Actions if no mis-prediction/exception (1) write
  result to register/memory, (2) update register
  status, (3) de-allocate the ROB entry
• Actions if with mis-prediction/exception flush
  the pipeline, e.g. (1) flush IFQ (2) clear
  register status (3) flush all RS and reset FU
  (4) reset ROB

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Example

• while (A(i) ltgt x)
• A(i)
• i
• Loop LD R2,0(R1) R1 base address of A()
• DADDIU R2,R2,1
• SD R2,0(R1) store result
• DADDIU R1,R1,4
• BNE R2,R3,LOOP x R3

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Non-Speculative executionDual issue, 2 CDB, 2
Int Units
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB
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Non-Speculative executionDual issue, 2 CDB (Gap
b/w Issue and Execute)
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB
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Speculative executionDual issue, 2 CDB