Barrier Layers Technology

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Barrier Layers Technology

• Prof. Yosi Shacham-Diamand
• Department of Physical Electronics
• Tel-Aviv University,
• Tel-Aviv 69978 ISRAEL

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Outline

• Introduction
• Copper Interconnect technology
• Barrier layers - overview
• Process development and integration
• Barrier layers modeling
• Barrier analysis, testing monitoring
• Summary

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Introduction

• Structure of Microchips
• ULSI metallization technology
• Metallization roadmap
• Downscaling issues
• Performance issues
• Manufacturing issues
• Where is the bottom ?

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Copper multi-level metallization
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IBM CMOS 7S process
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Copper chips...

• IBM power PC 750
• Mitsubishi Electric eRAMTM family
• AMD K7(Athalon)
• UMC 0.18 mm process
• Motorola 333MHz SRAM
• Lucent Chartered 0.16 mm process

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IBM PowerPC 750
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Structure of microchips
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ULSI metallization technology
????? 2000
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Gate and Interconnect delays
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Delay modeling - the barrier effect

• The specific resistance (rb ) of the barrier
  layers is higher than that of the Cu, (rCu)

W
H
Without barrier
L line length
With barrier (tb barrier thickness)
Assumption complete barrier coating
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Cu Damascene interconnect resistivity
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Effect of the barrier layer on the interconnect
delay
Interconnect delay Tint RintCint - including
the barrier. In the case of a Damascene
technology
For rb gtgt rCu we get the the interconnect delay
increases as the ratio between the actual copper
line cross section and the total cross section.
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Barrier layers - overview
Why do we need barriers ? Requirements from
barriers
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Barrier layers for Cu metallization

• Why do we need barrier layers?
• Copper affects Si properties
• Cu affects SiO2 properties
• Cu affect most insulators properties
• Cu adheres poorly to bottom and side ILD
• Why do we need a top barrier (capping layer)
• Cu corrodes
• Cu adheres poorly to top ILD

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Requirements from barrier layers

• Step coverage on high aspect ratio holes and
  trenches
• Low thin film resistivity
• Adhesion to the ILD
• Adhesion to Cu
• Stable at all process temperatures
• Process compatible to the ILD
• Process compatible to CMP
• Act as a good barrier

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Barrier layers - types

• Sacrificial
• Stuffed - impurities in the grain boundaries
• Amorphous - no grain boundaries

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Diffusion barrier - classification of the
candidates for barriers that has been
investigated in the last 15 years

• transition metals
• transition metal alloys
• transition metal - silicon
• transition metal nitrides, oxides, or borides
• Miscellaneous ternary alloys, a-carbon, etc.

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Summary of barrier layer classification

• Transition metals fail as barrier at lower
  temperatures than their nitrides
• transition metal silicides fail due to the
  reaction of the Si with the Cu. The reaction is
  most likely to happen at the grain boundaries
• Amorphous barriers offer very high reaction
  temperatures, however, they have very high
  specific resistivity
• The barrier properties depend also on the
  deposition method.

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Process development and manufacturing
considerations
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Step coverage issues
Barrier layer too thick
Barrier layer too thin
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Coverage issues

• Nonuniform sidewall deposition
• agglomeration
• Bad coverage at the bottom corner - can be
  amplified if the bottom corner has some overetch
  of the layer below

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The effect of pre-deposition clean on the barrier
integrity
Physical process in Ar ions Reactive
clean

• Problems
• Damage to the barrier
• Damage to the dielectric
• Barrier metal and Cu
• Sputtering and re-deposition on the sidewalls

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Copper patterning

• Dry etch
• Difficult, expensive
• Conventional equipment
• Dual Damascene
• Fully planar, lower cost,
• New technology

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Cu process options
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Electroplating solutions

• Cu ions - Cu sulfate
• Acid - H2 SO4 for pH adjustment
• HCl - Affects Cu surface adsorption Halide
  ad-layer drives Cu growth. It also acts as a
  surfactant and stabilizes grain growth. Cu
  deposition is driven by the desorption of the
  halides.

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Electroplating Based Process Sequence
Pre-clean IMP barrier Copper
Electroplating CMP 25 nm
10-20 nm 100-200
nm
Simple, Low-cost, Hybrid, Robust Fill Solution
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Diffusion barrier for Copper (I)

• PVD Ta,TiN, and TaN
• Neutrals sputtering
• Collimated Non collimated
• Ions sputtering
• RF ionized
• HCM- Hollow Cathode Magnetron
• CVD of TiN
• Iodine or Chlorine based chemistry
• CVD of Ta and TaN (or both)
• Bromide based chemistry
• MOCVD of TiN
• TDMAT TDEAT

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PVD barrier technologies
RF
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Diffusion barrier comparison, (M. Mossavi et al.,
IITC 98)
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Vias with IMP TaN
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Sputtered WxN barrier
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MOCVD TiN Precursors Tetrakis-dimethylamino
Titanium
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Other Novel barriers
RuO2 r40-250 mW cm TaSiN,TiSiN r200-600
mW cm WBN r300-10000 mW cm CoWP r20-120
mW cm
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Electroless barriers
Surface activation methods
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Advantage of Electroless barriers

• Conformal
• Low cost
• Good quality - low r, low stress
• can be integrated with electroless copper

Barrier Cu ILD
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Co(W,P) barrier layer
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Specific resistivity vs. solution composition
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Barrier layers modeling

• Diffusion models - kinetics
• Reaction models - thermodynamics

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Equilibrium thermodynamics of diffusion barriers
(C.E. Ramberg et al., Microelectronics
Microengineering, 50 (2000) 357-368)

• Cu makes silicides with silicon
• Barriers include transition metalmetaloid
  (Si,B,or N)

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Ternary phase diagrams

• The lack of Ta-Cu compounds yield a broad range
  of compositions in equilibrium with Cu.
• Ti-rich compositions are expected to react with Cu

N
TaN Ta2N
Ti
Cu
Ta
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Barrier Analysis monitoring

• Materials science techniques
• AES, SIMS, RBS, SEM
• Electrical characterization
• I-V
• C-V C-t

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Electrical characterization MOS capacitors
Capacitance measurements CV Flat band voltage,
interface states Ct minority carrier lifetime,
surface recombination velocity IV It
metal/insulator integrity.
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Ideal MOS capacitance-voltage curve. Solid curve
- High f , Dotted curve Low frequencies. Oxide
thickness is 140. NA 11015 cm-3.
Low frequency
High frequency
Relaxation
High frequency - fast sweep
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Example test of CoWP barrier layers
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CV characteristics of MOS capacitor with a.
Co(W,P)/Co and b. Co(W,P)/Cu/Co(W,P)/Co
metallization after 300ºC 30 min. and 520ºC for
2 hours anneal. (A 3.5710-4 cm2).
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C-t curves of Co(W,P)/Cu/Co(W,P)/Co/SiO2
capacitors annealed at 400C, 500C and 520C.
Device area is 3.5710-4 cm2.
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Generation lifetime, tg (sec), and Surface
Recombination velocity, So, (cm/sec)
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Copper profiles as measured by AES. The
sputtering rate was 12A/min for Co(W,P) on Cu,
25 A/min for Cu, 10A/min for Co(W,P) on Co,
8A/min for the sputtered Co.
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Barrier monitoring techniques
X-Ray fluorescence (XRF) - thickness and
composition (accurate, 5-10 points / min) X-Ray
reflection Thickness (Most accurate, 2-5
points / min)) Ellipsometry Thickness (low
accuracy, fast) Resistivity Others.?..?
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X-Ray reflectivity - Sputtered TiNdBarrier30.5
nm, r5.2 gr./cm3
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References

• Shi-Qing Wang, Diffusion barriers for Cu
  metallization on Silicon, Proceedings of the
  advanced metallization conference, MRS
  publications, San-Diego, 1993.
• The proceedings of the Advanced metallization
  conferences from 1993 to 1999
• The proceedings of the Workshop for Advanced
  Metallization (MAM) from 1997 and 1999
• Papers in various journals such as the Journal of
  electrochemical society, Journal Vac. Sci.Tech.,
  J. of Appl. Phys., J. Material research and more.

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Conclusions

• Dominant barriers for Cu technology are Ta (IMP),
  TaN (IMP) TiN (CVD)
• There are still problems, especially in high
  aspect ratio features
• Other barriers are under study (amorphous,
  electroless, etc.)
• Barrier technology is an enabling technology for
  ULSI metallization