Semiconductor Technology Basics

1
Semiconductor Technology Basics
2
Why Semiconductors?

• Conductors always have a high concentration of
  electrons in conduction bands
• states that are free to move through the material
• Insulators always have virtually zero electrons
  in such bands
• conduction band energy is too high
• all the electrons are stuck in valance bands
• localized to particular atoms/molecules in the
  material
• Semiconductors have a conduction band whose
  electron population is easily manipulated
• Sensitive to dopants, applied potentials,
  temperature

3
Electronic Structure of Silicon

• Silicon, atomic number 14
• sp orbitals of shell 3 are (together) half full
• Like in Carbon (element 6), s,p orbitals can
  rearrange to form four sp3 hybrid orbitals w.
  tetrahedral symmetry
• Each Si can share electrons with 4 neighboring
  Sis to fill all the 3sp orbitals... Stable
  tetrahedral lattice, like diamond

1s
2s
3s
2p
3p
4
Electrons Holes

• At normal temperatures,
• a small percentage ofshell-3 electrons will be
  free of the bond orbitals
• wandering thru the lattice
• leaving a hole in the lattice point they left
• a hole acts like a positively charged particle
• Once created, holes can move, too
• by a nearby electron hopping over to fill them
• however, hole mobility is usually lower than that
  of electrons

5
Donor Acceptor Dopants

• Boron (element 5) is one electron shy of having a
  half-empty shell 2 that would fit Si lattice
• Boron atoms readily accept extra mobile electrons
  and lock them in place, forming a negative B- ion
• Reduces free-electron concentration, increases
  hole concentration when implanted into silicon
• Phosphorus (element 15) has one too many shell-3
  electrons to fit in Si lattice
• Donates the extra electronreadily to conduction
  band
• Increases free-electron conc., decreases hole
  conc.

1s
2s
3s
2p
3p
Forms P ion
1s
2s
3s
2p
3p
6
p-type vs. n-type Silicon

• Pure silicon
• Has an equal number of positive negative charge
  carriers (holes electrons, resp.)
• Acceptor-doped (e.g., boron-doped) silicon
• Has a charge-carrier concentration heavily
  dominated by positive charge carriers (holes, h)
• Balanced by negative, immobile ions of acceptor
  atom
• We call it a p-type semiconductor.
• Donor-doped (e.g., phosphorus-doped) silicon
• Has charge-carrier concentration heavily
  dominated by negative charge carriers (electrons,
  e-)
• Balanced by positive, immobile ions of donor atom
• Call it n-type semiconductor

7
pn junctions

• What happens when you put p-type and n-type
  silicon in direct contact with each other?
• Near the junction, electrons from the n and holes
  from the p diffuse into annihilate each other!
• Forms a depletion region free of charge carriers

Depletion region
p-type
n-type
h
h
h
e-
e-
e-
e-
e-
e-
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h
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pn junction electrostatics
Depletion region
cf. Pierret 96
h
h
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e-
e-
e-
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e-
e-
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e-
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h

Charge density
?
Electric field
Built-involtage
Electrostatic potential
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npn MOSFET (n-FET)
Metal-Oxide-SemiconductorField-EffectTransist
or
Vbias
gateelectrode
n
n
p
Potential as seenby electrons
Electronpotentialenergy(negative
ofelectricpotential)
p
p
p
p
e?
e?
e?
e?
e?
e?
e?
e?
e?
p
p
p
p
e?
e?
e?
When Vbias gt 0
e?
e?
e?
e?
e?
e?
e?
e?
e?
Gate voltage gt Vt
10
CMOS Inverters
(a) CMOS inverter structure. (b) Transition
curves.
11
Semiconductor Technology Scaling
12
(Sources 1994-1999 SIA/ITRS roadmaps, 1997
lecture by Gordon Moore)
13
(Source ITRS 2000 Update)
14
(source ITRS 01 roadmap)
.08 ?m already available
Intel has verified20 nm transistorsin the lab
NOW
15
Technology Scaling Notation

• Historically, device feature length scales have
  decreased by 12/year.
• So feature length ? ? 0.88year ? ?
• 1/? ? (1/0.88)year ? 1.14 year ? ?
• up 14/year
• Meanwhile, typical CPU die diameters have
  increased by 2.3/year. (Less stable trend.)
• Diameter ? 1.023year ? ?
• 1/Diameter ? 0.978year ? ?
• Quantities that are constant over time are
  written as ? 1 ? ?

16
Some 1st-order Semiconductor Scaling Laws

• Voltages V?? (due to e.g. punch-through )
• Long-term temperature T?? (prevents leakage)
• Resistance
• Fixed-shape wire R ? ?/wt ? ?/?? ?
• Thin cross-chip wire R? ?/?? ???
• Capacitance
• Fixed-shape structure C ? ?w/s ? ??/? ?
• Per unit wire length C ? ? (constant)
• Cross-chip wire C ? ?
• Per unit area C ? 1/s ? ?

17
Why Voltage Scaling?

• For many years, logic voltages were maintained at
  standard levels as transistors shrunk
• TTL 5V logic - standard for many years
• later 3.3 V, now 1V within leading-edge CPUs
• No longer possible, due to various effects
• Punch-through
• Device degradation from hot carriers
• Gate-insulator failure
• Carrier velocity saturation
• Things break down at high field strengths
• constant-field scaling may be preferred

18
Punch-Through
p
p
p
p
Zero bias
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
Moderate bias
e?
e?
e?
e?
e?
e?
Strong bias
e?
e?
e?
e?
e?
e?
e?
e?
Very strong bias
19
Need for Voltage Scaling
n
n
p
p
p
p
p
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
e?
Smaller size same voltage ?higher electric
field strengths ?easier punch-through
20
Long-term Temperature Scaling?

• May be needed in the long term.
• Standby power dissipation across off transistors
  is based on the leakage current density ? exp(-Vt
  / ?T)?
• Vt is the threshold voltage
• Must scale down with Vdd, or else transistor
  cant turn on!
• ?T is the thermal voltage at temperature T
• Equal to kBT/q, where q is electron charge
  magnitude
• Voltage spread of individual electrons fr.
  thermal noise
• As voltages decrease,
• leakage power will dominate
• devices will become unable to store charge
• Unless (eventually), T ? V ? ? ? ?
• Only alternative Scaling halts!
• Probably what must happen, because low
  temps.imply slow rate of quantum evolution.

Unfortunately,lower T ? fewercharge carriers!
21
Resistance Scaling

• Fixed-shape wire (any shape) R ? ?/wt ? ?/??
  ?
• All dimensions scalingequally.
• E.g. a local interconnectin a small scaled
  logicblock / functional unit
• Constant-length thin wire R? ?/?? ??
• Thin cross-chip wire R? ?/?? ??? !
• Up 33/year!
• Long-distance wires have to be extra thick to be
  fast
• But, fewer thick wires can fit!

?
t
w
Current flow
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Capacitance Scaling
w
?

• Fixed-shape structure (any) C ? ?w/s ? ??/? ?
• E.g. scaled devices/wires
• Per unit wire length
• C ? ?w/s ? ??/? ? ? (constant)
• Cross-chip thin wire C ? ?
• Per unit area C ? ??/s ? ?
• E.g., total on-chip cap./cm2

s
23
Delay Scaling

• Charging time delay t ? RC
• Through fixed shape conductor RC ? ?? ?
• Thin constant-length wire RC ? ??
• Via cross-die thin wire RC ? ???? up 36/yr!
• Through a transistor RC ? ?? ?
• Implications
• Transistors increasingly faster than long thin
  wires.
• Even becoming faster than fixed-shape wires!
• Local communication among chip elements is
  becoming increasingly favored!

24
Performance scaling

• Performance characteristics
• Clock frequency for small, transistor-delay-domina
  ted local structures f ? 1/t ? ? (up 14/yr)
• Transistor density (per area) d 1/?? ??
• Perf. density RA fd ??? chip area A ? ??
• Total raw performance (local transitions / chip /
  time) R fd A ????? 1.55year
• Up 55/year!
• Nearly doubles every 18 months (Moores Law).
• Raw perf. has so far been harnessed for
  performance improvements in serial microprocessor
  performance.
• Future architectures may need to move to more
  parallel programming models to fully use further
  improvements.

25
Charges Currents

• Charges fields
• Charge on a structure Q CV ? ??
• Surface charge density Q/A ? ?
• Electric field strengths E V/? ? ?
• Currents
• Peak current densities J E/? ? ?
• Peak current in a wire I JA ? ??
• Channel-crossing times t ?/v ? ?
• Due to constant e? saturation velocity v ? 200
  kmph
• Current in an on-transistor I Q/t ? ??/? ?
• Effective trans. on-resistance R V/I ? ?/? ?

Resistivity Constant
26
Interconnect Scaling

• Since transistor delay dt scales as ?,
• And wire delay dw (w. scaled cross-section size)
  for a wire of length ? scales as RC ?
  (?/wt)(?w/s) ?2/st ? ?2/?? ?2??,
• Then to keep dw lt dt (1-cycle access)
  requires ?2?? lt ? ?2 lt ?/?? ??? ? lt ?3/2
• So wire length in units of transistor length ?t
  is ?/?t lt ?3/2/? ?1/2 (down 6/year)
• So number of devices accessible within a constant
  dt in 2-D goes as (?1/2)2 ?, in 3-D as
  (?1/2)3 ?3/2.
• Circuits must be increasingly local.

27
Energy and Power

• Energy
• Energy on a structure E ? QV ? CV2 ? ??2 ?3
• Energy per-area EA ? CV2/A ? ?3/?2 ?
• Energy densities E/?3 ? ?3/?3 ? ? (not a
  problem)
• Power levels
• Per-area power PA EAf ? ?? ? (not a problem)
• Power per die P PAA ? ?? (up 5/year)
• Power-per-performance PA/RA ?/??? ???
• But, if constant-field scaling is not used (and
  it has not been, very much), all the above
  scaling rates get increased by the square of the
  field strength (F) scaling rate.
• Since V ? F?, and E and P scale with V2.

28
3-D Scalability?

• Consider stacking circuits in 3-D within a
  constant volume.
• of layers n ?/thickness ? ?/? ? ?
• Total power PT P(flat chip)n ? ?? ?
• Enclosing surface area AE ?
• Power flux (if not recycled) PT/AE ?/? ?
• For this to be possible, coolant velocity, /or
  thermal conductivity must also increase as ?!
• Probably not feasible.
• Power recycling is needed to scale in 3-D!

29
Semiconductor Technology Limits
30
Types of Limits

• Meindl 95 identifies several kinds of limits on
  VLSI (from most to least fundamental)
• Theoretical limits (focus on energy delay)
• Fundamental limits (such as we already discussed)
• Material limits (dependent on materials used)
• Device limits (dependent on structure geometry)
• Circuit limits (dependent on circuit styles used)
• System limits (dependent on architecture
  packaging)
• Practical limits
• Design limits
• Manufacturing limits

31
Fundamental Limits

• Thermodynamic limits
• Minimum dissipation per bit erasure
• kT ln 2 limit. More stringent limits for
  reliability coming up.
• Subthreshold conduction leakage currents
• Ion/Ioff ? exp(Vdd / ?T)
• Quantum mechanical limits
• Tunnelling leakage currents (cf. Mead 94, next
  slide)
• Energy-time uncertainty principle ?E ? h/?t
• Related to Margolus-Levitin bound tnop
  ½h/(E-E0)
• Electromagnetic limits
• Speed-of-light lower bound on delay for an
  interconnect of a given length, t ?/c.

32
Tunneling Limit on Device Size

• This graph plots the de Broglie wavelength ?
  h(2mE)-1/2 of electrons of effective mass m
  having kinetic energy equal to barrier height E.
• This is also the min. barrier width neededto
  prevent electron tunneling with probability
  greater than 3.510-6.

33
Material Limits

• Carrier mobility (carrier velocity/field
  strength)
• Affects carrier velocity, on-current, transition
  time
• 6x higher in GaAs than in Si, but only at low
  field
• Carrier saturation velocity (max velocity)
• Nearly equal for Si and GaAs.
• Velocity maxes out _at_ 100 nm/ps
• Occurs _at_ 1-10 V/?m in Si (depends on doping)
• Breakdown field strength Ec
• 33 higher in GaAs than Si
• Thermal conductivity next slide
• Dielectric constants slide after

34
Thermal Conductivity

• For a given device structure, P ? K ?T
• P - rate of heat removal (power)
• K - thermal conductivity of materials used
• ?T - how much hotter is device than its
  surroundings
• 3x lower for GaAs than for Si
• Implies GaAs is 3x slower when speed is limited
  by conductive cooling through substrate (often
  true)!
• Highest known K Diamond!
• K2 mW/?mK, 14 times higher than Silicon!
• Can be a semiconductor if Boron-doped, or an
  insulator if not.
• Also has high mobility, high breakdown voltage,
  good tolerance for high-temperature operation.
• NTT recently demonstrated a diamond semiconductor
  capable of 81 GHz frequencies in analog
  applications.
• Apollo Diamond in MA is developing a cheap
  manufacturing capability for single-crystal
  diamond wafers using CVD.

35
Dielectric Constants

• Dielectric constants ? ?/?0 C/C0. ?SiO2 ? 4
• Want high ? in thin gate dielectrics,
• To maximize channel surface-charge density,
  thus on-current, for given VG,on,
• But avoid very low thickness w. high tunneling
  leakage.
• Material must also be an insulator! (?SrTi
  310!)
• Want low ? for thick interconnect insulators
• To minimize parasitic C and delay of
  interconnects
• Lowest ? possible is that of vacuum (1). Air is
  close.

36
Some Device Limits

• MOSFET channel length
• Generally, the lower, the better!
• Reduces load capacitance thus load charging
  time.
• But, lengths are lower-bounded by the following
• Manufacturing limits, such as lithography
  wavelengths.
• Supply voltage lower-limits to keep a decent
  Ion/Ioff.
• Depletion region thickness due to dopant density
  limits.
• Yield, in the face of threshold variation due to
  statistical fluctuation in dopant concentrations.
• Source-to-drain tunneling.
• Distributed RC network response time
• Limited by
• ? of wires (e.g. the recent shift from Al to Cu)
• ? of insulators (at most, 4x less than SiO2 is
  possible)
• Widths, lengths of wires limited by basic
  geometry

37
Circuit Limits

• Power supply voltage limits (later)
• Switching energy limits (later)
• Gate delays
• Fundamentally limited by transistor
  characteristics, RC network charging times
• each of which are limited as per previous slide
• There is a fastest possible logic gate in any
  given device technology
• esp. considering it has to be switched by similar
  gates
• Static CMOS its close relatives (precharged
  domino, NORA) are probably close to the
  fastest-possible gates using CMOS transistors in
  a given tech. generation.

38
System Limits

• Well discuss these more later in the course
• Architectural limits
• Power dissipation
• Heat removal capability of packaging
• Cycle time requirements
• Physical size

39
Design Design-Verification Limits

• Increasing complexity ( of devices/chip) leads
  to continual new challenges in
• Design organization
• modularity vs. efficiency
• Automatic circuit synthesis layout
• circuit optimization
• Design verification
• layout-vs-schematic
• logic-level simulation
• analog (e.g. SPICE) modeling
• Testing and design-for-testability
• test coverage

40
Manufacturing Limits

• See the ITRS 01 roadmap for these.
• Lithography resolution, tools
• Dopant implantation techniques
• Process changes for new device structures
• Assembly packaging
• Yield enhancement
• Environmental / safety / health considerations
• Metrology (measurement)
• Product cost factory cost

Red brick wall could be reached as early as
2003! --ITRS 01
41
Possible Endpoints for Electronics

• Merkles minimal quantum FET
• Mesoscale nanoelectronic devices based on metal
  or semiconductor islands
• E.g. Single-electron transistors, quantum dots,
  resonant tunnelling transistors.
• Organic molecular electronic devices
• diodes, transistors
• Inorganic atomic-scale devices
• 1-atom-wide chains of conductor/semiconductor
  atoms precisely positioned on/in substrates
• Also discuss Superconducting devices

42
Energy Limits in Electronics

• Origin of CV2/2 switching energy dissipation
• Thermal reliability bounds on CV2 scaling
• Voltage limits
• Capacitance limits
• Leakage trends in MOSFETs

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44
Limit on Switching Energy

• Consider temporarily connecting a single unknown
  bit to ground.
• Average dissipation is 1/4 CV2.
• At least T log 2 dissipation required to erase
  bit by Landauers principle.
• Therefore, CV2 ? 4T log 2 4kBT ln 2.

0/1?
0
0
CV2/4
Entropylog 2
Entropylog 1 0
45
Reliability w. Thermal Noise

• Consider N logic nodes, 1 of which is high.
• Dont know which Entropy log N.
• Then, connect them all to ground temporarily.
• Want them all to be 0, with high probability.
• Logical entropy is now 0.
• Log N entropy must be exported elsewhere.
• Requires T log N expenditure of energy.
• But, only ½CV2 energy was dissipated!
• So, to reliably do N arbitrary irreversible bit
  operations requires at least ½CV2 ? T log N kBT
  ln N energy per logic node.

46
Illustration of Scenario
0
0
0
0
0
0
1
0
0
CV2/2
N
0
0
0
0
0
0
0
0
0
Entropy0
Entropylog N
½CV2 ? T log N
47
On/Off Ratio from State Count

• The theoretical maximum FET on/off ratio
  is Ion/Ioff Rmax exp(V/fT).
• However, note that we can simplify
• That is, the maximum on/off ratio equals the
  number Nelec of distinct single-electron states
  between the Fermi levels for on and off gate
  states!
• If this analysis is correct, it would mean there
  is a minimum entropy generation for FET based
  switching of 1 bit!

V gate voltage swing
Eelec potential energy difference per electron
Ielec change in gate info.content per electron
Nelec number of single-electronstates between
1 and 0 levels
48
Thermal Capacitance

• What is the minimum entropy generation for a
  structure of given capacitance C?
• Consider minimal node voltage V (ln R)fT
• Needed to get desired on/off ratio of R.
• Let the thermal capacitance CT qe/?T.
• At room temperature CT 6 aF.
• Then we can derive an expression for minimum
  entropy generation for our structure
• S ? ½(log N) C/CT
• This implies that C ? 2(ln N) CT at minimum V.

49
Voltage Bounds for Reliability

• Suppose we are stuck with a given C. Then the
  minimum voltage that we can tolerate is
• One implication If some nodes have C less than
  thermal capacitance, then voltages cannot
  actually approach the thermal voltage.
• Other lower bounds on node voltages
• V ? ?T - to switch FETs strongly on off
• V gtgt ?VT - to avoid defects due to threshold
  variation

50
In Particular Generations

• Year 2001 technology, aggressive low-power
• 9 knats per transistor-switching op
• Year 2012 projection
• 2 knats
• 30x whats needed for 1e27 reliability (ln N60)
• 1e9 nodes lasting 1e9 seconds at 1e9 hertz w/o
  error