VLSI System Design Methodologies

1
VLSI System Design Methodologies

• Md. Shabiul Islam
• Lecture - 2
• Multimedia University

2
Topics

• Basic fabrication steps.
• Transistor structures.
• Basic transistor behavior.
• Latch up.

3
Fabrication services

• We need to study fabrication processes and the
  design rules that govern layout. We will use as
  our example the SCMOS rules, which have been
  defined by MOSIS, the MOS Implementation service.
• Similar services, such as Euro Chip/Euro Practice
  in the European Community, VDEC in Japan, and CIC
  in Taiwan, serve educational VLSI needs in other
  Countries.

4

• Educational services
• U.S. MOSIS
• EC EuroPractice
• Taiwan CIC
• Japan VDEC
• Foundry fabrication line for hire.
• Foundries are major source of fab capacity today.

5
Fabrication processes

• A cross section of an integrated circuit is shown
  in Figure in next page. Integrated circuits are
  built on a silicon substrate. Components are
  formed by a combination of processes
• The n-type and p-type regions can be used to make
  wires as well as transistors, but polysilicon (
  which is also used to form -

6

• Transistor gates) and metal are the primary
  materials for wiring together transistors because
  of their superior electrical properties.
• IC built on silicon substrate
• some structures diffused into substrate
• other structures built on top of substrate.

7

• Substrate regions are doped with n-type and
  p-type impurities. (n heavily doped)
• Wires made of polycrystalline silicon (poly),
  multiple layers of aluminum (metal).
• Silicon dioxide (SiO2) is insulator.

8
Simple cross section
SiO2
metal3
metal2
metal1
poly
substrate
n
n
p
substrate
9
Photolithography

• Features are patterned on the wafer by a
  photolithographic process the wafer is covered
  with light-sensitive material called
  photoresist,which is then exposed to light with
  the proper pattern.

10
Process steps

• Transistors are fabricated within regions
• called tubs or wells
• First place tubs to provide properly-doped
  substrate for n-type, p-type transistors

11
Process steps, contd.

• Pattern polysilicon before diffusion regions

gate oxide
poly
poly
p-tub
p-tub
12
Process steps, contd

• Add diffusions, performing self-masking

poly
poly
p-tub
p-tub
n
n
p
p
13
Process steps, contd

• Start adding metal layers

metal 1
metal 1
vias
poly
poly
p-tub
p-tub
n
n
p
p
14

• Figure in next page shows the cross-section of
  n-type MOS transistor. An n-type transistor is
  embedded in a p-type substrate it is formed by
  the intersection of an n-type wire and a
  polysilicon wire.
• The region at the intersection , called the
  channel, is where the transistor action takes
  place.

15
Transistor structure

• n-type transistor

16
0.25 micron transistor (Bell Labs)
gate oxide
silicide
source/drain
poly
17
Transistor layout

• Example The basic layout of an n-type (tubs may
  vary) transistor is simple This layout is a
  minimum-size transistor. Current flow through the
  channel vertically.

18
Drain current characteristics
19

• Vgs the gate to source voltage
• Vds the drain to source voltage
• Idthe current flowing between the drain and
  source.
• Vt the transistor threshold voltage, which is
  positive for an n-type transistor and negative
  for a p-type transistor
• W/L the width to length ratio of the transistor.

20
Drain current

• For an n-type transistor, we have,
• Linear region (Vds lt Vgs - Vt)
• Id k (W/L)(Vgs - Vt)(Vds - 0.5 Vds2)
• Saturation region (Vds gt Vgs - Vt)
• Id 0.5k (W/L)(Vgs - Vt) 2

21
0.5 ?m transconductances

• From a MOSIS process
• n-type
• kn 73 ?A/V2
• Vtn 0.7 V
• p-type
• kp 21 ?A/V2
• Vtp -0.8 V

22
Current through a transistor

• Use 0.5 ?m parameters. Let W/L 3/2. Measure at
  boundary between linear and saturation regions.
• Vgs 2V
• Id 0.5k(W/L)(Vgs-Vt)2 93 ?A
• Vgs 5V
• Id 1 mA

23
Basic transistor parasitics

• Real devices have parasitic elements which are
  necessary artifacts of the device structure.
  Since the transistor is a non-linear device, we
  are primarily concerned with its capacitance as
  parasitics, although the source and drain regions
  have significant resistance.

24
Basic transistor parasitics

• Gate to substrate, also gate to source/drain.
• Source/drain capacitance, resistance.

25
Basic transistor parasitics, contd

• Gate capacitance Cg. Determined by active area.
• Source/drain overlap capacitances Cgs, Cgd.
  Determined by source/gate and drain/gate
  overlaps. Independent of transistor L.
• Cgs Col W
• Gate/bulk overlap capacitance.

26
Latch-up

• CMOS ICs have parastic silicon-controlled
  rectifiers (SCRs).
• When powered up, SCRs can turn on, creating
  low-resistance path from power to ground. Current
  can destroy chip.
• Early CMOS problem. Can be solved with proper
  circuit/layout structures.

27
Parasitic SCR
circuit
I-V behavior
28
Parasitic SCR structure
29
Solution to latch-up

• Use tub ties to connect tub to power rail. Use
  enough to create low-voltage connection.

30
Tub tie layout
p
metal (VDD)
p-tub