VLSI System Design Methodologies

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VLSI System Design Methodologies

• Md. Shabiul Islam
• Lecturer, Faculty of Engineering
• Multimedia University
• 63100 Cyberjaya, Selangor
• Malaysia
• Email shabiul_at_mmu.edu.my

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Contents

• 1. Chapter Lecture-1
  Page
• 1.1 Why VLSI 3
• 1.2 Moores Law 4
• 1.3 The Cost of Fabrication 6
• 1.4 The VLSI Design Process 8
• 1.5 Challenges in VLSI design 9
• 1.6 Dealing with Complexity 12
• 1.7 Hierarchical Name 13
• 1.8 Layout and its abstractions 20

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Conti.

• 1.9 Stick diagram 20
• 2.0 Transistor Schematic 24
• 2.1 Levels of Abstraction 28
• 2.2 Top-down Vs. bottom-up design 32
• 2. Chapter Lecture-2
• 2.1 Fabrication services 3
• 2.2 Fabrication processes 5
• 2.3 Basic Transistor parasitics 23

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Conti...

• 3. Chapter Lecture-3
• 3.1 MOSFET gate as Capacitor 3
• 3.2 Body effect 6
• 3.3 Channel length modulation length -
• parameter 9
• 3.4 Leakage and subthreshold current 11
• 3.5 Circuit simulation 15

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Conti.

• 4. Chapter Lecture-4
• 4.1 Wires and Vias 3
• 4.2 Metal migration 4
• 4.3 Wire resistance 11
• 4.4 Mean-time-to-failure 12
• 4.5 Skin effect 13
• 5. Chapter Lecture-5
• 5.1 Why we need design rules 3
• 5.2 Manufacturing problems 4
• 5.3 MOSIS SCMOS design rules 9

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Conti...

• 5.4 Lamda design rules 10
• 5.5 Stick diagrams 18
• 5.6 Layout design and analysis tools 25
• 6. Chapter Lecture-6
• 6.1 Combinational logic expressions 3
• 6.2 Gate Design 5
• 6.3 Boolean algebra terminology 6
• 6.4 Static complementary gates 8
• 6.7 Pullup/Pulldown network design 18

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Conti...

• 7. Chapter Lecture-7
• 7.1 Standard cell layout 3
• 7.2 Routing Channels 9
• 7.3 Example Full adder layout 14
• 7.4 Layout methodology 15
• 7.5 Left-edge algorithm 18
• 7.6 Simulation 24

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Conti...

• 8. Chapter Lecture-8
• 8.1 Sources of delay 3
• 8.2 Fanout 6
• 8.3 Path delay 11
• 8.4 Delay model 15
• 8.5 Logic Optimization 22
• 9. Chapter Lecture-9
• 9.1 Transistor Sizing 3
• 9.2 Carry Chain Optimization 6
• 9.3 Logical effect 11

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Conti...

• 9.4 Effort delay 13
• 10. Chapter Lecture-10
• 10.1 Memory elements 3
• 10.2 Dynamic latch 8
• 10.3 Clocked inverter 18
• 10.4 Flip-flops 23
• 10.5 Sequential machines 26

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Conti...

• 11. Chapter Lecture-11
• 11.1 Flip-flop-based sequential machines 3
• 11.2 Strict two-phase clocking discipline 9
• 11.3 Signal types 15
• 11.4 Two-coloring 20
• 11.5 Example Shift register 21
• 11.6 Qualified Clocks 25

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Conti...

• 12. Chapter Lecture-12
• 12.1 Combinational Shifters 3
• 12.2 Barrel Shifter 5
• 12.3 Analysis 11
• 12.4 Manchester Carry Chain 22
• 12.5 ALUs 26
• 13. Chapter Lecture-13
• 13.1 Elementary School algorithm 3
• 13.2 Combinational multiplier 5
• 13.3 Booth encoding 11

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Conti..

• 13.4 Wallace tree 15
• 13.5 Serial-Parallel multiplier 18
• 14. Chapter Lecture-14
• 14.1 High-density memory architecture 3
• 14.2 Memory operation 4
• 14.3 Read-Only memory 6
• 14.4 Static RAM 9
• 14.5 3-transistor DRAM 15

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Conti...

• 14.6 Data paths 19
• 14.7 Bit-slice structure 21
• 14.8 PLA 27
• 15. Chapter Lecture-15
• 15.1 Floorplanning Strategics 3
• 15.2 Bricks-and-mortar floorplan 6
• 15.3 Types of routing 8
• 15.4 Block placement 11
• 15.5 Channel definition 14

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Conti...

• 15.6 Windmills 24
• 15.7 Slicable fllorplan 26
• 15.8 Global routing 28
• 16. Chapter Lecture-16