LECTURE 10 DIGITAL ELECTRONICS

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LECTURE 10 DIGITAL ELECTRONICS
Dr Richard ReillyDept. of Electronic
Electrical EngineeringRoom 153, Engineering
Building
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Basic Inverter

• The inverter is the basic circuit with which most
  MOS logic circuits are developed.
• DC and Transient analysis
• Design methods developed for the inverter can
  easily be extended to NOR and NAND gates.
•  

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Basic Inverter

• These load elements can be compared on the
  following Inverter Analysis basis
• DC Voltage Transfer Characteristics
• Noise Margins
• Propagation Delay
• Power Dissipation
• Circuit Density

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Basic Inverter

• The basic NMOS inverter circuit

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Static NMOS Inverter Analysis

• Consider a single NMOS transistor connected with
  a resistor load to form an inverter.

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Voltage Transfer Characteristic

• The resistor current is equal to the NMOS drain
  current
• can be expressed as a function of VDS.
•  
• A linear relationship between ID and VDS for a
  constant RL.

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Voltage Transfer Characteristic

• This suggests that the voltage transfer function
  characteristic can be obtained graphically
• HOW ?
• by superimposing the output load (resistor) line
  over the NMOS ID vs. VDS family of
  characteristic
• with VGS as a parameter.
• Each value of VGS VIN for the inverter gives a
  different drain characteristic curve

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Voltage Transfer Characteristic

• Ordered pairs of points (VGS, VDS) are read from
  the intersection of the output load line with the
  family of curves.
• These are in turn plotted on VDS vs. VGS
• VTC is the resulting curve through these points.
• Gives a value of VDS VOUT for one value of
  input voltage.
• ? can plot VOUT vs. VIN

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Voltage Transfer Characteristic

• Drain Characteristics and Resistor Load Line

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Voltage Transfer Characteristic

• When a logic 1 represented by VOH appears at the
  input of this inverter
• transistor is driven in conduction along upper
  line of drain I-V characteristic
• with proper design logic low level VOL falls
  below transistor threshold voltage
• ? a following inverter stage will be
  non-conducting

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Voltage Transfer Characteristic

• This qualitative analysis gives an insight into
  the operation of Q0 for the resistor loaded NMOS
  inverter.
• In the output state, Q0 turns on in the
  saturation region of operation.
• For the output low state Q0 is in the linear
  region
• The state of the Q0 can be determined for the
  other critical points also.

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Active Load

• The 100k? resistor in the example above is needed
  to limit power consumption.
• It would require a large amount of chip area if
  realised in a standard MOS process
•  
• Sheet resistances available in standard processes
  are in the range 20-100? per square.
• Assuming 100? per square
• A resistor width of 5 ?m
• ? RL would be 5000 ?m long
• ? It would occupy an area 100 times that of the
  transistor

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Active Load

• But the required resistor
• Where often called the aspect
  ratio.
•  
• However if the transistor aspect ratio
  is increased to reduce the size of RL
• proportional increase in transistor size and
  operating current
• One solution is to use small area, high valued
  resistors formed by additional special processes
•   Only used in some LSI systems, never in VLSI

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Active Load

• The alternative way is to use small transistors
  to perform the function of a load resistor.
•  
• Enhancement-mode NMOS transistors can be used as
  load elements operating in either saturation or
  linear regions.
• Were the only forms of transistor load in
  single-polarity MOS circuits before depletion
  mode transistors became feasible with
  ion-implementation in the 1970s.
• Better circuit performance and smaller circuit
  area are obtained using depletion mode NMOS
  transistors as load elements.

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Active Loads

• Alternative load elements to Resistive Loads
• Saturated Enhancement Mode Loads
• Linear Enhancement Mode Loads
• Depletion Mode Loads

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Saturated Enhancement Load

• A single NMOS transistor can be used as a load
  device
• with gate connected to drain
• Note The body is grounded as it is common to
  all transistors in a single chip.

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Saturated Enhancement Load

• Because VGS VDS
• load transistor can operate only in either
  saturation and cut-off.
• i.e. VDS VGS gt VGS - VT

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Saturated Enhancement Load

• QUESTION
• What is the value of ? for an enhancement-mode
  load transistor, with VT 1 so that it will
  provide the same current for VDD 5V, VOL 0.3V
  as the 100k? resistor described in the
  resistor load case above ?.
• where K 20?A/V2 and
• the inverter has an aspect ratio of 2.0.

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Saturated Enhancement Load

• As the load transistor is in saturation
•  
•  
• ?

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Saturated Enhancement Load

• The load line construction and the VTC for the
  inverter with this enhancement load are
• Drain Characteristic and Load Line

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Saturated Enhancement Load

• Voltage Transfer Characteristic

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Saturated Enhancement Load

• ?
• ? This is larger than the inverter device.
•  
• If the minimum allowed dimension is
• The inverting device has aspect ratio of 2 ?
• ? The load device will have and

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Geometry or Beta Ratio

• From equation
• both and scale linearly with the drain
  current ID in the load.
•  
• Because of this fact
• ? the aspect ratio for each transistor
  may be multiplied by the same factor without
  affecting voltage levels.
• Of course operating current will be multiplied by
  the same factor

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Geometry or Beta Ratio

• The geometry or beta ratio for a MOS device
  inverter is defined as
•  
• If the designer is free to adjust the operating
  current of inverters and gates
• ? a minimum area layout will usually be achieved
  with device size chosen so that the geometric
  mean of the inverter and load aspect ratio
  is unity
• By reducing the value of also reduces the
  circuit area.

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Geometry or Beta Ratio

• One serious deficiency of the enhancement load
  has been overlooked so far.
• The output high level VOH is no longer equal to
  VDD as it was for the resistor load.
• The load transistor ceases to conduct after its
  gate source voltage decreases to the threshold
  voltage
• ? in this case the output mode does not rise
  above
• ? the threshold voltage of the load device is no
  longer as it is for the inverter
• as the full output voltage appears as a body-bias
  between the source and body of the load device

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Geometry or Beta Ratio

• The threshold voltage is now given by
• A recomputation shows that the value of
  needed to achieve is considerably
  increased if is reduced from 5 to 3.5 V.
• These circumstances make it difficult to design
  simple enhancement load static inverters and
  gates which will operate with safe noise margins
  on a 5V supply.

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Linear Enhancement Load

• From the analysis of the saturated load inverter
• Output node can rise to a threshold drop below
  VDD before the load devices ceases to conduct.
• i.e.
•  
• The output voltage of an enhancement-only loaded
  NMOS inverter can be raised to VDD by using a
  load that operates in the linear region.
• Can be accomplished by applying a separate larger
  voltage source to the gate of the load
  transistor.
• This is one reason why early MOS circuits
  required higher voltage supplies.

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Linear Enhancement Load
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Linear Enhancement Load

• To operate in the linear region
• ?
•  
• ? The gate voltage should satisfy
•  
•  
• Thus the circuit is a linear enhancement loaded
  NMOS inverter when the above condition is met.
• ? load device operates in the linear region over
  the entire range of VOUT.
• ? since throughout this range the load device
  is operating with
•  

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Linear Enhancement Load

• The load line construction for this type of
  inverter
• Drain Characteristic and Load Line

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Linear Enhancement Load

• Voltage Transfer Characteristic

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Linear Enhancement Load

• Many different names are applied to this mode of
  operation
• linear load - despite the considerable
  curvature to the load line
• non-saturated load
• triode load
•  
•  
• The linear-enhancement load has several
  disadvantages when used in static inverters and
  gates
• More chip area is required, since extra voltage
  source VGG with associated additional
  interconnections on the chip are needed.

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Depletion load

• Depletion loads overcome the disadvantages
  described above
• At the relatively minor expense of special masked
  ion-implementation step to create the depletion
  device.
• So-called enhancement-depletion (E-D) NMOS
  technology is the basis for the most
  microprocessors and microprocessor peripheral
  devices and static NMOS memories.

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Depletion load

• I-V characteristics of the ideal and a practical
  depletion load device.
• Drain Characteristic and Load Line

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Depletion load

• A constant current source would be the ideal load
  device
•   Because the full static load current would be
  available to charge the load capacitance from VOL
  to VOH when the inverter input changes from high
  to low.

Voltage Transfer Characteristic
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Depletion load

• An IDEAL depletion device with Gate connected to
  Source (VGS0)
• Approaches current source performance
•  
• Unlike the Saturated enhancement and Linear
  enhancement loaded NMOS inverters
• where devices operate only in the saturated or
  linear mode
• The depletion loaded NMOS inverter operates in
  either the saturated or linear mode.

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Depletion load

• With the VT negative
• ? hence load device is always
  active
•  
• Whether the region of active operation is linear
  or saturated is determined by
•  
• If this inequality is true ? Load device in
  saturation
• Otherwise load device in linear region
•  
•  
• and

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Depletion load

• For
• inverter is cut-off
• no drain current in either transistor
•  
• Since no drain current ? Load device must be in
  the linear region of operation.
• can be calculated by solving
  the linear drain current expression.

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Depletion load

• This gives
• And thus
•  
•  With no body effect ? upper load line, where
  load device is in saturation
•  
• Consider a practical depletion load with normal
  body effect.
• With ?0.37 (typical value)
• serious degradation in load device
  characteristics.
•  
• Why ?
• body bias effect make VTdep more positive
• drain current for the depletion load decreases as
  VOUT rises

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Geometry or Beta Ratio

• As have seen in a custom layout of a VLSI design
  in NMOS, not all devices have the same
  dimensions.
•  
• Depletion mode devices are used as load elements
• to simply the fabrication process
• to provide greater current when the inverter
  device is first turned off and a capacitive load
  must be charged.
• When VGS (Vin) is low and the capacitive load is
  charged.
• ? output VOUT will be approximately VDD,
  regardless of the device dimensions.

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Geometry or Beta Ratio

•  
• If VGS is logical 1 (VDD)
• current flows in both enhancement and depletion
  devices.
• output will assume some voltage VOL
• must be less then VT to be regarded as a logical
  0
• If VOL lt VT, then inverter is operating in the
  linear region.
•  
• The voltage across the load device is large,
  VDD-VOL
• ? device is in saturation region.

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Geometry or Beta Ratio

•  
• Substituting VTdep for the threshold voltage in
  saturated current expression
• ?
•  
• The current in the inverter device can be found,
  where VOL is substituted for VDS.

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Geometry or Beta Ratio

• Since VOUT will drive the gates of other MOS
  devices that have an infinite input impedance in
  the steady state
• neglecting , solving for VOL with
  Vdep -0.8VDD
• ? where

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Geometry or Beta Ratio

• ? let VGS VDD
• and assume that the typical enhancement mode
  VTinv 0.2VDD
• ?
• If the condition that
  0.1VDD is made
• ?
• ? we have a simple but fundamental relationship
  on the geometries of the inverter and load device
  in the NMOS depletion-loaded inverter.

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Switching Time Analysis and Power Product Delay

• Total Capacitance
• Have discussed earlier that each MOS transistor
  has five separate voltage
• dependent capacitance coupling its four
  electrodes.
• Analysis of MOS transistors circuits in which
  each capacitor is considered is virtually
  impossible.
•  
• However, analysis of approximate switching times
  becomes feasible if all capacitance effects are
  lumped into a single total capacitor, CT that is
  connected to the output node of each inverter or
  gate.

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Switching Time Analysis and Power Product Delay

• Device capacitances in a circuit comprising two
  cascaded inverters can be lumped at the inverter
  output nodes.
• Cascaded NMOS inverters only capacitances to be
  included in analysis are included

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Switching Time Analysis and Power Product Delay

• Lumped Capacitances at Inverter Output

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Switching Time Analysis and Power Product Delay

• The current available to charge and discharge CT
  are the drain currents from the inverter and load
  devices.
• A true situation, in which, VIN and VOUT are both
  changing with time while satisfying the
  non-linear DC device equations, is simulated
  point-by-point in the time domain by SPICE or
  equivalent.
• However with suitable simplifications, a 1st
  order approximation is possible

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Propagation Delay Times

• Considering the NMOS inverter circuits, when the
  input makes an idealised instantaneous change
  from VOH to VOL
• Inverter transistor fails to turn off while the
  load current continues to flow.

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Propagation Delay Times

• The time taken for VOUT to charge from VOL to the
  50 point can be calculated
• calculated by assuming the lumped load
  capacitance is charged by a constant current
  equal to the average current through the load
  device.
• Calculation of the actual load current is rather
  complex
• Different for every choice of load device.
• Approximation can be made by considering the two
  currents at the endpoints of the voltage
  transmission.

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Propagation Delay Times

• The approximate average capacitor charging
  current ILH(av) is found by simply averaging the
  load device current at
• the propagation delay can then be calculated as
• In this case the propagation delay is

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Propagation Delay Times

• Just after the input makes an idealised
  instantaneous change from VOL to VOH
• ? both inverter and load device are conducting
• current available to discharge the load
  capacitance from VOH to the 50 point is the
  difference between the inverter and load device
  currents.
•  
• These currents can be calculated separately for
  each device at VOH and at the 50 point.

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Propagation Delay Times

• Then IDLoad is subtracted from IDInv at each
  endpoint to obtain the net current available to
  discharge the load capacitance.
• The two net currents are used to obtain an
  approximate average value IHL(av).
•  
• the time for the transition from VOH to the 50
  point is calculated in the same manner as above.
• The average propagation delay is defined as

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Summary

• Need to be conscious when designing ICs of area
  and power.
• Resistive loads (necessary for baising and path
  for current) are very wasteful of area and power.
• Use MOS transistors as load elements.