Silicon Design Page 1

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The Creation of a New Computer Chip
2
The Concept
A group of people from marketing,
design, applications, manufacturing and finance
develop the basic concept, features and rough
specifications for a new product.
3
They all go off and work on their
particular pieces of the proposal
Marketing what are the customers asking for
and what will sell vs. the competition,
what is the marketing plan,
what will it cost
Design how will it be designed, how long will
it take, what design tools will be
necessary, how many people will it take, what
will it cost
Manufacturing how will it be manufactured, what
tooling will be
necessary, how many manufacturing
lines will it need, what will it cost
Finance will the product make money, what is
the return on investment, what
resources are available and what
will need to be acquired, what will it cost
4
The Decision
They all get back together again with management
and decide whether or not to proceed will the
project.
5
GO!
Once the decision is made to proceed, the design
team swings into action
6
The Design Flow
Block Level
RTL Level
RTL Simulation
Logic Level
Logic Simulation
Transistor Level
Extract Parasitics create timing model
Physical Layout Level (masks)
7
The Block Diagram
The problem is broken down into basic functions
blocks and the interfaces are specified
Branch Control
I/O
8
The High Level Description
The blocks are then broken down into functional
units and registers. The functionality is coded
in a high level descriptive language. This is
known as the RTL description.
Register File
operand selection and register control
IR
ALU control
master control
ALU
9
The High Level Simulation
The RTL description is simulated to ensure that
the design performs as it should.
10
The Logic Level Description
The functional units are then broken down into
logic gates and registers. This is known as the
logic level description.
11
The Logic Level Simulation
The logic description is simulated to ensure that
the design performs as it should. It is also
compared against the RTL simulation.
12
The Transistor Description
The logic gates are broken down to
their component transistors. From this
description, the timing delays and electrical
parasitics can be estimated. If necessary,
transistors can be resized.
OR
N type
P type
Field Effect Transistors
13
Field Effect Transistor Operation
P type
N type
Gate Ground 0
14
Field Effect Transistor Operation
P type
N type
Gate Vcc 1
15
N Type Field Effect Transistor
no current flow
GND
P type substrate
Silicon Wafer
GND
16
N Type Field Effect Transistor
Vcc
P type substrate
Silicon Wafer
GND
17
N Type Field Effect Transistor
Vcc
P type substrate
Silicon Wafer
GND
18
N Type Field Effect Transistor
current flow
Vcc
P type substrate
Silicon Wafer
GND
19
P Type Field Effect Transistor
no current flow
Vcc
Vcc
N-Well
P type substrate
Silicon Wafer
GND
20
P Type Field Effect Transistor
GND
Vcc
N-Well
P type substrate
Silicon Wafer
GND
21
P Type Field Effect Transistor
GND
Vcc
N-Well
P type substrate
Silicon Wafer
GND
22
P Type Field Effect Transistor
current flow
GND
Vcc
N-Well
P type substrate
Silicon Wafer
GND
23
Logic Gate Implementation Using Field Effect
Transistors
24
So how do we build Field Effect Transistors?
We start with a blank piece of silicon wafer
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
25
Cover it with an N-well Mask
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
26
Bombard it with negatively charged ions to create
the N-well
N type dopant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
27
Create the N-well
N type dopant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
28
Create the N-well
N type dopant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
29
Grow the Gate Oxide layer
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
30
Grow the Gate Oxide layer
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
31
Deposit Polysilicon
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
32
Cover it with a Polysilicon mask
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
33
Etch the Polysilicon and Oxide
Etchant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
34
Etch the Polysilicon and Oxide
Etchant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
35
Etch the Polysilicon and Oxide
Etchant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
36
Etch the Polysilicon and Oxide
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
37
Cover it with an N Transistor mask
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
38
Implant the N type Dopant
N type dopant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
39
Implant N Dopant
N type dopant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
40
Cover it with a P Transistor mask
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
41
Implant P Dopant
P type dopant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
42
Implant P Dopant
P type dopant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
43
Grow more Oxide
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
44
Grow more Oxide
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
45
Cover it with a Contact mask
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
46
Etch the Oxide
Etchant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
47
Etch the Oxide
Etchant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
48
Deposit Metal
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
49
Deposit Metal
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
50
Cover it with a Metal mask
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
51
Etch the Metal
Etchant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
52
Etch the Metal
Etchant
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
53
Deposit Insulation
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
54
Deposit Insulation
P type substrate
P type substrate
P type substrate
P type substrate
Silicon Wafer
Silicon Wafer
Silicon Wafer
Silicon Wafer
55
A CMOS Inverter
56
N-well Mask
57
Polysilicon Mask
58
N Transistor Mask
59
P Transistor Mask
60
Metal Mask
61
Contact Mask
62
The Completed Circuit
Vcc
N-well
OUT
Gnd
IN
63
Partial Die Plot
64
More Partial Die Plots
65
Complete Chip Plot
Intel Microcontroller Chip 80C196KJ
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Another Chip Plot
67
Intel Pentium 4
68
Processed Silicon Wafer
69
Processed Silicon Wafer
A wafer
A die
70
Wafer Fabrication

• Preceding steps done in a wafer fab
• Silicon wafer fabrication facility
• Fabs are expensive
• rely on high volumes to get part cost down

71
Post-Wafer Fabrication

• Each die is tested to see which work
• Wafer is cut up
• Good die are kept
• Bad die are thrown away

72
Packaging
73
Packaging
74
Packaging
75
Packaging
76
Packaging
77
Packaging
78
Final Testing

• Packaged chips are tested again
• Burn-in used to eliminate infant mortality
• Good chips labelled and shipped