Lecture 5 Combination Logic Design

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Lecture 5 Combination Logic Design

• Pradondet Nilagupta
• pom_at_ku.ac.th
• Department of Computer Engineering
• Kasetsart University

2
Acknowledgement

• This lecture note has been summarized from
  lecture note on Introduction to VLSI Design, VLSI
  Circuit Design all over the world. I cant
  remember where those slide come from. However,
  Id like to thank all professors who create such
  a good work on those lecture notes. Without those
  lectures, this slide cant be finished.

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Topics

• Combinational logic functions.
• Static complementary logic gate structures.

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Combinational logic expressions

• Combinational logic function value is a
  combination of function arguments.
• A logic gate implements a particular logic
  function.
• Both specification (logic equations) and
  implementation (logic gate networks) are written
  in Boolean logic.

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Gate design

• Why designing gates for logic functions is
  non-trivial
• may not have logic gates in the libray for all
  logic expressions
• a logic expression may map into gates that
  consume a lot of area, delay, or power.

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Boolean algebra terminology

• Function
• f ab ab
• a is a variable a and a are literals.
• ab is a term.
• A function is irredundant if no literal can be
  removed without changing its truth value.

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Irredundancy

• A logical expression is irredundant if no literal
  can be removed from the expression without
  changings its value
• Redundant expressions
• ab a
• ab ab'
• Irredundant expressions
• ab' a'b
• a cd'

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Completeness

• A set of logical functions is complete iif we can
  generate every possible Boolean function using
  that set
• The set AND, OR, NOT is complete
• The set NAND is complete
• The set AND, OR is not complete
• Transmission gates are not complete.
• If your set of logic gates is not complete, you
  cant design arbitrary logic.

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Minimality

• A logic expression is minimal if no equivalent
  form has a higher cost (i.e., literal count)
• Minimality ? Irredundancy
• CAD tools are available to find the minimal (or
  near-minimal) form for
• Two level logic (AND/OR Sum of Products)
• Multilevel Logic (Arbitrary network of gates)

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Static complementary gates

• Complementary have complementary pullup (p-type)
  and pulldown (n-type) networks.
• Static do not rely on stored charge.
• Simple, effective, reliable hence ubiquitous.

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Static complementary gate structure

• Pullup Network - drives output to VDD
• Pulldown Network - drives output to GND

VDD
VDD
Pullup
Network
(p-transistors)
Inputs
Out
In
Out
Pulldown
Network
(n-transistors)
Gnd
Inverter
Gnd
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Inverter layout

(tubs not shown)
out
a
a
out
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Complementary CMOS Notes

• Pullup, pulldown networks should NEVER conduct at
  same time!
• Pullup, pulldown networks are duals
• Parallel in pulldown implies serial in pullup
• Serial in pulldown implies parallel in pullup
• Gate Types
• Simple NAND, NOR, inverter
• And-Or-Invert (AOI)
• Or-And-Invert (OAI)

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Layout Considerations

• Metal lines required for Vdd!, Gnd!
• ndiff, pdiff must be separated by 10 lambda
• Transistor options
• horizontal or vertical diffusion lines
• Start with minimum-size transistors
• Increased width implies increased driving
  capabilitiy, but
• Do the analysis first to see if its necessary

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Layout Considerations (cont'd)

• Interconnect layers (use vias when necessary)
• Metal 1
• Metal 2
• Poly
• Diffusion
• Specify a well depending on process type
• Use substrate contacts to prevent latchup

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NAND gate

out
b
a
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NAND layout
VDD

out
out
tub ties
b
a
b
a
GND
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Layout Example - NAND

• Compare to Fig 3-10, p. 122
• Differences from Magic
• Explicit contact cuts
• P-tub as well as N-tub
• Larger N-well
• Note transistor sizes
• Note substrate contacts

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NOR gate

b
a
out
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NOR layout
VDD
b
a
tub ties
b
out
out
a
GND
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Layout Example - NOR

• Compare to Fig 3-12, p. 123
• Differences from Magic
• Explicit contact cuts
• P-tub as well as N-tub
• Larger N-well
• Note transistor sizes
• Note substrate contacts

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Layout - Creating Wide Transistors

• Divide into multiple transistors
• Tie together sources, drains
• Compare to Fig 3-9, p. 121
• Missing but still needed substrate contacts

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AOI/OAI gates

• AOI and/or/invert OAI or/and/invert.
• Implement larger functions.
• Pullup and pulldown networks are compact smaller
  area, higher speed than NAND/NOR network
  equivalents.
• AOI312 and 3 inputs, and 1 input (dummy), and 2
  inputs or together these terms then invert.

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AOI example

• out abc

invert
symbol
circuit
or
and
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Pullup/pulldown network design

• Pullup and pulldown networks are duals.
• To design one gate, first design one network,
  then compute dual to get other network.
• Example design network which pulls down when
  output should be 0, then find dual to get pullup
  network.

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Dual network construction
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Inverter - DC Analysis
in
out
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Inverter DC Analysis - Continued
Note dependence on bn/bp Recall
Source N. Weste K. Eshraghian, Principles of
CMOS VLSI Design Addison Wesley, 1992
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Logic Levels Output

• Logic values are represented by a range of
  voltages
• Logic 1 between VOH and VDD (5V)
• Logic 0 between VOL and VSS (0V)
• Static CMOS Output levels
• VOH VDD (5V)
• VOL VSS Gnd (0V)

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Logic Levels Input

• Examine DC Input/Output Curve (Fig 3-15, p. 120)
• Pick points where slope -1 as VIL , VIH
• Rationale compare change in VIN , VOUT
• VIN lt VIL - small change in VIN causes small
  change in VOUT
• VIN gt VOUT - small change in VIN causes small
  change in VOUT
• VIN lt VIL lt VIH - small change in VIN causes
  large change in VOUT

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Logic Levels - Summary
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Noise Margin

• A measure of noise immunity
• Logic 1 NMH VOH - VIH
• Logic 0 NML VOL - VIL
• Important when noise is present
• Definition small random variations in voltage
• Dont want noise to affect circuit output

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Transistor Sizing and Noise Margin

• Changing beta (size) ratio changes VIH, VIL
• To balance noise margin
• Make bnbp gt Wp3.5Wn
• Actually, Wp2Wn is often good enough

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Gate Delay

• Consider an inverter with "step function" input
• Delay related to time to discharge / charge CL

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Simplifying Assumptions

• Assume transistors turn on/off instantaneously
• Model transistor as a switch, resistor in series
• Resistor approximates Vds/Id at different values
  of Vds
• (See Fig. 2-6, p. 45 Fig 3-17, p. 123, Fig. 3-18,
  p. 123)
• Use average of Vds/Id at
• middle of linear region Vlin 0.5(Vds - Vss -
  Vt)
• maximum of saturation region Vsat (Vds - Vss)

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Delay Calculation - Finding Rn
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Delay Calculation - Finding Rn
Table 3-1, p. 125 (0.5µm process, VDD5V) Rn
3.9k? Rp 14k?
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Gate Delay (cont'd)

• Equivalent Network - see p. 125
• Eq. 3-6 voltage vs. time
• Eq. 3-7 solve for 90-10 time
• Delay calculation - assuming loading of a single
  inverter p. 106

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Fall Time Approximation

• Capacitor initially charged at VDD
• Transistor approx. Rn
• Fall time (90-10) tf 2.2 Rn CL

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Rise Time Approximation

• Capacitor initially discharged (at Vss)
• Transistor approx. Rp
• Fall time (90-10) tp 2.2 Rp CL

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Gate Delay Accuracy

• Comparison to Spice simulation Fig 3-19, p. 127
• Estimate seems overly conservative, BUT
• Step functions don't occur in "real life"
• Spice simulation of cascaded inverters Fig.
  3-20, p. 128
• First inverter output a more realistic waveform
• Second inverter delay comparable to estimate

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Gate Delay of NAND Gate

• Pulldown series n-transistors tf 2.2 (2
  Rn) CL
• Pullup parallel p-transistors (worst case when
  one on) tr 2.2 Rp CL

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Gate Delay of NOR Gate

• Pulldown parallel n-transistors (worst case
  when one on) tf 2.2 Rn CL
• Pullup series p-transistors tr 2.2 (2
  Rp) CL
• NOR slower than NAND (why?)

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Gate Delay

• Consider an inverter with a rising input
• Delay related to time to discharge / charge CL

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Gate Delay - Definitions
Delay time to reach 50 of final value tpHL
(book calls this td) tpLH Transition Time time
between 10 and 90 tf - fall time tr -
rise time
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Simplifying Assumptions

• Assume Step Function input
• Model transistor as switch and resistor
• Resistor approximates Vds/Id at different values
  of Vds
• Use average of Vds/Id at
• middle of linear region Vlin 0.5(Vds - Vss -
  Vt)
• maximum of saturation region Vsat (Vds - Vss)
• Book calls this the t model

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Delay Calculation - Finding Rn
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Delay Calculation - Finding Rn
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Delay Calculation - Finding Rp
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Delay Calculation - Finding Rp
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Summary Calculating Rn and Rp

• Assume VSS0 to simplify

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Example Calculating Rn

• Use values from book

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Example Calculating Rp

• Use values from book

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Summary Rn and Rp for Minimum-Sized Transistors
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Inverter Delay with the t model
Rising Input / Falling Output
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Inverter Delay with the t model
Falling Input / Rising Output
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NAND Gate Delay with the t Model

• Fall time n-transistors in series
• tf 22.2(RnRL)CL
• Rise time 1 p-transistor on (for worst case)
• tf 22.2(RnRL)CL

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NOR Gate Delay with the t Model

• Fall time one n-transistor on(worst case)
• tf 2.2(RnRL)CL
• Rise time p-transistor in series
• tf 22.2(RnRL)CL

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AOI Gate Delay with the t Model

• Fall time 2 n-transistors in series(worst case)
• tf 22.2(RnRL)CL
• Rise time 3 p-transistors in series(worst case)
• tf 32.2(RnRL)CL

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Delay Estimation - Other Approaches

• Current source model - treat transistor as
  current source in saturation
• Fitted model
• Measure several circuit characteristics fit to
  formula
• Used in CAD tools
• Circuit Simulation - Most accurate approach

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Accuracy of methods

• Comparison to Spice simulation Fig 3-20, p. 133
• t Model
• Current Source Model
• What to do
• Use simple models for
• Quick prediction of delay
• Insight into circuit operation
• Comparison of different circuits
• Use Spice for accurate simulation

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Example - Inverter Delay

• Estimate tr and tf for a minimum-size inverter
  driving the inputs of four minimum-size
  inverters(assume loading only from transistor
  gates)

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Example - Inverter Delay (1/2)

• Estimate loading from a single inverter

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Example - Inverter Delay (2/2)

• Now use Rn, Rp, CL to calculate tr, tf

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Example - Gate Delay of an AOI Gate

• Use values in book for VDD5V
• Rise time tr
• Worst case 2 transistors in series
• Fall time tf
• Worst case series connection

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Effect of Increased Transistor Width

• Increase width of transistor to
• Increase current
• Reduce effective resistance (Rn or Rp)
• Side-effect increased input capacitance(more
  about this later)

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Example Gate Delay of a NOR (VDD5V)
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Transistor Sizing Example

• Size the transistors in an inverter so that trtf
• Rp / Rn 13K? / 3.9K? 3.47
• Make Wp approximately 3.5Wn

W10 L2
W3 L2
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Transistor Sizing Example

• Size the transistors in an AOI gateso that trtf
• Rp / Rn 13K? / 3.9K? 3.47(round down to 3)
• Size each worst case path for equal delay
• Assume L2 in all transistors

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18
36
18
6
3
6
6
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Result of Body Effect Increased Delay

• Consider n-transistors in series
• T1 has higher Vt while C1 charged
• T1 turns on more slowly
• CL discharges more slowly
• Delay (fall time) increases!
• What to do?
• Attempt to reduce parasitic C1-internal node
  capacitance
• Place earliest-arriving gate inputs near Gnd
  (VDD, for p-transistors)
• Place latest-arriving gate inputsnear output

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Body Effect

• Weve used fixed values for Vtp, Vtn, BUT
• This is true only if source/substrate voltage
  Vsb0
• Not always the case when transistors are in
  series
• Increasing Vsb
• increases width of depletion layer
• raises the threshold voltage Vt
• Example (p. 56) if Vsb5V, ?Vt0.16V (24 of Vt)

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Power Consumption

• Static power consumption - due to leakage current
• Diode leakage - reverse-biased diode junction
• Subthreshold current - in deep submicron
  devices
• Total static consumption
• Dynamic power consumption
• Power consumed as outputs switch to
• Charge load capacitances
• Discharge load capacitance

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Dynamic Power Consumption

• Charging Capacitor
• Current, voltage Eq. 3-8, 3-9 (p. 130)
• Energy Eq. 3-10
• Discharging Capacitor
• Current, voltage Eq. 3-11, 3-12 (p. 131)
• Energy Eq. 3-13

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Power Consumption (cont'd)

• Power Energy per unit time
• P fCL(VDD-VSS)2 fCLVDD2
• Where
• f rate of change of gate output
• Worst case ffclock (more likely f lt fclock but
  f a fclock )
• P depends only on f, CL, and VDD!
• For overall chip
• P fCL(VDD-VSS)2 fCLVDD2

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Power Consumption and VDD

• Reducing VDD creates large reduction in P
• If we reduce VDD to VDD,

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Delay and VDD

• Tradeoff reducing VDD increases delay
• If we reduce VDD to VDD,
• Tradeoff reducing VDD decreases noise immunity
  (more careful design necessary!)

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Design Strategies for Power Reduction

• Use lower VDD to reduce power
• Compensate for higher delays by
• Using newer, smaller, faster IC technology
• Trading off more slower logic for less faster
  logic - this is called voltage scaling
• Examples (from Tom Burds General Processor
  Information)
• Intel P5 Pentium VDD5.0V / fclk66MHz / P16W
• Intel P54C VDD3.3V / fclk100MHz / P5.0W
• Intel P55VRT VDD3.3 / fclk200Mhz / P3.4W
• Intel P6 VDD3.3V/ fclk166MHz / P23.4W
• Compaq Alpha 21264 VDD2.0V / fclk667MHz /
  P72W

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Speed-Power Product

• A way of characterizing the quality of a logic
  family
• For static complementary CMOS
• Bottom line easiest way to reduce power is to
  reduce VDD