Self_Biasing PLL Design

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Self_Biasing PLL Design

• Peiqing zhu

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VCO design

• 8-stages delay cell

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Simulation result
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VCO Design(2)-4 stages delay cell
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Simulation result_1
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Simulation result_2
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OPamp Design
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Simulation result_1
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Simulation result_2
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Simulation result of biasing generator and
4_stages VCO
Output swing voltage1.1v Idc3.6mA for every
delay cell. F2.6Ghz
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Simulation result of biasing generator and
8_stages VCO
Output swing voltage1.1v Idc3.6mA for every
delay cell. F1.3Ghz
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Simulation result of biasing generator and
12_stages VCO
Output swing voltage1.1v Idc3.6mA for every
delay cell. F0.866Ghz
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Simulation result of biasing generator and
4_stages VCO
Output swing voltage0.7v Idc0.9mA for every
delay cell. F1.345Ghz
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Simulation result of biasing generator and
8_stages VCO
Output swing voltage0.7v Idc0.9mA for every
delay cell. F0.660Ghz Now we can update this
frequency to 1.3GHz in the new version
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Conclusion

• 1)VCO using 4_stages has some distortions but
  has a higher speed (up to 2.6GHz)
• 2)VCO using 8_stages has no distortion but has a
  lower speed (up to 1.3GHz)
• 3)VCO speed is limited by the charge or
  discharge capacitance time.

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VCO delay cell
Parasitic capacitance
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8_Stages VCO Schematic
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8_Stages VCO Layout
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8_Stages VCO Post Layout Simulation
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Opamp_Design
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Simulation Result
3dB bandwidth 1.67Ghz
Phase Margin 54deg
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VCO Design-delay cell design
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8_Stages VCO Design
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VCO output frequency1.30GHz
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VCO Simulation Result
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Biasing Generator and VCO
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Simulation Setup for the VCO
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Simulation Result
Output frequency1.24GHz
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VCO GAIN
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Charge Pump Design
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Charge Pump Design Xor gate
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Xor Simulation Result
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S2D Module Design
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S2D Simulation Result_100MHz Input signal
S2D Module Simulation Result
INPUT SIGNAL
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S2D Simulation Result_200MHz Input signal
INPUT SIGNAL
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XOR2 Design_Version2
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XOR2 Simulation Result
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S2D Modulator
XOR2
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Simulation Result For the S2D
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Charge Pump Design_1
Ibiasing3.619mA
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Charge Pump Simulation Result_1
When IDN pulse width is 5ns /10ns and IUP pulse
width is 1ns/10ns
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Charge Pump Simulation Result_2
When IDN pulse width is 3ns /10ns and IUP pulse
width is 1ns/10ns
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Charge Pump Simulation Result_3
When IDN pulse width is 1ns /10ns and IUP pulse
width is 3ns/10ns
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Charge Pump Simulation Result_4
When IDN pulse width is 1ns /10ns and IUP pulse
width is 5ns/10ns
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Charge Pump Simulation Result_5
When IDN pulse width is 1ns /10ns and IUP pulse
width is 1ns/10ns
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Charge Pump Simulation Result_6
When IDN pulse width is 3ns /10ns and IUP pulse
width is 3ns/10ns
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PFD Design
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PFD Schematic
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PFD Simulation Setup
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PFD Simulation Result
When the data input frequency200MHz,and dclock
frequency190MHz
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PFD Simulation Result
When the data input frequency190MHz,and dclock
frequency200MHz
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PFD Simulation Result
When the data input frequency200MHz,and dclock
frequency200MHz
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Diff2Single Converter
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D2S Simulation Setup
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Simulation Result_1
When the input signal frequency2GHz
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Simulation Result_2
When the input signal frequency2.5GHz
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Simulation Result_3
When the input signal frequency3GHz
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D2S Schematic
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Simulation Result_1
When the input signal frequency1.5GHz
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Simulation Result_2
When the input signal frequency2GHz
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Simulation Result_3
When the input signal frequency2.5GHz
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Simulation Result_4
When the input signal frequency3GHz
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Divided_By_20 Circuit Design
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Divider_By_20 Schematic
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Schematic of Divided_By_4
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DFF in the Divider
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Simulation Result of Divided_By_4
When input signal frequency1GHz
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Simulation Result of Divided_By_4
When input signal frequency2GHz
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Simulation Result of Divided_By_4
When input signal frequency3.3GHz
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Schematic of Divided_By_5
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Simulation Result of Divided_By_5
When input signal frequency500MHz
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Simulation Result of Divided_By_5
When input signal frequency1GHz
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Simulation Result of Divided_By_5
When input signal frequency2GHz
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The Schematic of Divider_By_20
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The Simulation of Divider_By_20
When input signal frequency1GHz
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The Simulation of Divider_By_20
When input signal frequency1.5GHz
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The Simulation of Divider_By_20
When input signal frequency2GHz
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The Simulation of Divider_By_20
When input signal frequency3.3GHz
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VCOD2S Design
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VCOD2S Schematic
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VCOD2S Schematic Simulation Result
When Vctrl1.2v,ie, the VCO output
frequency1.45GHz
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VCOD2S Schematic Simulation Result
When Vctrl1.3v,ie, the VCO output
frequency1.36GHz
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VCOD2S Schematic Simulation Result
VCO OUTPUT
D2S OUTPUT
When Vctrl1.4v,ie, the VCO output
frequency1.25GHz
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VCOD2S Schematic Simulation Result
When Vctrl1.5v,ie, the VCO output
frequency1.15GHz
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VCOD2S Schematic Simulation Result
When Vctrl1.6v,ie, the VCO output
frequency1.01GHz
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VCOD2SDivider Schematic
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VCOD2SDivider Simulation Result
When Vctrl1.2v,ie, the VCO output
frequency1.40GHz
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VCOD2SDivider Simulation Result
When Vctrl1.3v,ie, the VCO output
frequency1.31GHz
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VCOD2SDivider Simulation Result
When Vctrl1.4v,ie, the VCO output
frequency1.22GHz
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VCOD2SDivider Simulation Result
When Vctrl1.5v,ie, the VCO output
frequency1.11GHz
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VCOD2SDivider Simulation Result
When Vctrl1.6v,ie, the VCO output
frequency0.989GHz
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PFDS2D Schematic
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PFDS2D Schematic Simulation Results
When Data signal leads the Clk signal, the UP
signal goes to high PW of data signal10ns,
and PW of CLK12.5ns, PW Pulse Width
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PFDS2D Schematic Simulation Results
When Data signal frequency is equal to the Clk
signal, the UP and DOWN signal goes to high _at_
same time. PW of data signal12.5ns, and PW of
CLK12.5ns
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PFDS2D Schematic Simulation Results
When Data signal frequency lags to the Clk
signal, the DOWN signal goes to high PW of
data signal12.5ns, and PW of CLK10ns
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PFDS2D Schematic Simulation Results
When Data signal leads the Clk signal, the UP
signal goes to high PW of data signal4.8ns,
and PW of CLK5ns, PW Pulse Width
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PFDS2D Schematic Simulation Results
When Data signal frequency is equal to the Clk
signal, the UP and DOWN signal goes to high _at_
same time. PW of data signal5ns, and PW of
CLK5ns
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PFDS2D Schematic Simulation Results
When Data signal frequency lags to the Clk
signal, the DOWN signal goes to high PW of data
signal5ns, and PW of CLK4.8ns
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Symmetric Resistor
Requvalent170ohm
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Loop Filter Design
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Start Up Circuit
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Start Up Circuit Simulation Result
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1.25GHz Self_Biasing PLL Schematic
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Self_Biasing PLL Simulation Result
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Self_Biasing PLL Simulation Result (Zoom In)
VCO DIFF OUTPUT
VCO Single End OUTPUT
DCLOCK
Vref Signal
Vcontrol Voltage
Lock time2.3us
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1.25GHz Self_Biasing PLL Schematic(modified_1)
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Self_Biasing PLL Simulation Result
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Self_Biasing PLL Simulation Result (Zoom In)
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1.25GHz Self_Biasing PLL Schematic(modified_2)
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Self_Biasing PLL Simulation Result
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Self_Biasing PLL Simulation Result (Zoom In)
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1.25GHz Self_Biasing PLL Schematic(modified_3)
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Self_Biasing PLL Simulation Result
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Self_Biasing PLL Simulation Result (Zoom In)
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1.25GHz Self_Biasing PLL Schematic(modified_8)
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Self_Biasing PLL Simulation Result
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Self_Biasing PLL Simulation Result (Zoom In_1)
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BiasingVCOD2S
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Simulation Results
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Startup_circuit