SystemC

1
Compatibility
Issues
and Efficiency
SystemC
in
by M. N. V. Satya Kiran Under the esteemed
guidance of Prof. M. Balakrishnan
Dr. J. F. M. Theeuwen Dept. of Computer
Science Engg.,
EDT Synthesis, Indian Institute of Technology,
Delhi Philips Research, Eindhoven
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Overview

• SystemC - What it is Why it is??
• Motivation
• Re-using TSS models in SystemC
• Extension to SystemC A Proposal
• Comparison between TSS and SystemC
• Abstract Communication Modeling A New
  Modeling Style
• Conclusions Future Work

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Introduction
Higher abstraction levels in Design
Modeling Intellectual Property (IP) re-use
exchange Interoperable system design
tools Specification Implementation
Unified and Standard Language
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System Level Design Language
Heterogeneous Models of Computation
Multiple Mixed abstraction levels
Describe both HW SW
Specification Implementation language
Application Architecture both before after
Mapping
Should support structure hierarchy
Constraints, Event ordering, Timing,
Dependencies, Concurrency, Reactivity, Scheduling
Algorithms
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SystemC
A open standard from Open SystemC Initiative A
C Class Library
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SystemC-2.0 Language Architecture
process of calling an interface method of a
channel
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Models of computation in SystemC
The model of time employed the event ordering
constraints Method of communication between
concurrent processes Rules for process activation
Static Multi-rate Dataflow Dynamic Multi-rate
Dataflow Kahn Process Networks Communicating
Sequential Processes Discrete event as used
for RTL HW modeling, Network modeling, Transact
ion based SoC modeling
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Motivation
TSS Tool for System Simulation SystemC can
replace TSS?? Simulation Speed?? All the past
developments (legacy code) will be
lost Developing all the models from the scratch
is difficult
A concept to re-use TSS models in
SystemC Comparison between TSS and SystemC
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Re-using TSS models in SystemC
Co-simulation
Adapter-based Approach
supports co-existence of TSS and SystemC SystemC
kernel with TSS user interface TSS source code is
not required only for simulation not for other
purposes poor performance
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Parser-based Approach
Objective
Method
tss_define_process(,TSS_DEL) -
SC_METHOD tss_add_sense_list() -
sensitive tss_declare_port() -
sc_portltgt tss_assign(port, expr) -
port-gtwrite(expr) IPORTV(port) -
port-gtread()
Viewports An interface to some part of internal
data of the model Performance Statistics Read
Write monitors can be set Ease debugging
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Parser-based Approach
JPEG A Case study
SystemC IPs plug play better
performance supported by many other
tools implementation of parser is bit
difficult TSS source code is required
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Extension to SystemC to support VHDL Delay
Modeling
X
wait(5, SC_NS) A 1
A lt 1 after 5 NS
Delta delay problems
sc_event contains only time e.notify(5,SC_NS)
Add value to sc_event along with
time e.notify(5, SC_NS, new_val)
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Comparison between TSS SystemC
Performance Comparison
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Problems to be addressed by New Modeling Style
Simulation validate systems at various design
steps
slow
Application Architecture Design Space
Exploration System Communication
Exploration Simulations - dynamic
behavior Execution cycles - validate design
choices Design alternatives - time-consuming
IP Re-use Communication is often intertwined
with computation - undesirable Behavioral IPs -
RTL IPs
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Signal accurate communication Models
Master
Master Slave
Master Cache
Slave
Master Slave Cache
Slave
BCU
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Objectives for New Communication Modeling Style
Speed-up of cycle accurate communication
minimum details about communication
architecture and protocol to enable Re-use
The intention of communication should be
clear generic to ease design exploration Able
to represent the whole system for cycle
accurate simulations
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Abstract Communication Modeling (ACM)
Model communication intention
Communication architecture and protocol -
communication controller
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System with Abstract Communication Models (ACMs)
Communication Controller
Communication Controller
Master Interface with put_req() Slave Interface
with read_data(), write_data() Cache Interface
with state_validate(), check_data(), get_data()
3-5 times faster than signal accurate
communication
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Data Structure addr, data, rbeats, obeats, bytes,
mode, state, ack, cycles, next_data
BFM_dataT dt Dt.addr addr Dt.rbeats
8 Dt.bytes 4 Dt.mode WWD READ
Mastport.Put_req(dt)
Semantics of blocking Wait for Whole Data Wait
for First Data Dont Wait for resource contention
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Features of ACM
Simple and easy to use, reduces model development
time Generic, ease communication
exploration Support arbitration, cache
coherency, pipeline operation, split
transactions, etc Support complex masters,
slaves and caches Support any type of
communication architecture, like shared bus,
multiple buses, interconnection network, etc
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Features of ACM
Support many of existing protocols (PI, AMBA,
etc) Support (or extensible to) new
communication protocols Can model system at
un-timed or partially cycle accurate or fully
cycle accurate Speed-up simulations Support and
encourages IP Re-use Extensible to support new
communication intentions
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Conclusions
A method to re-use TSS models in SystemC TSS
SystemC (3, 2, even faster) Modification in
SystemC kernel ACM reduces model development
time ACMs reusable and generic ACM speed-up
simulations ACM speed-up Design Space Exploration
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Future work
A library for SystemC, for the proposed
ACM Studying use of ACM in communication
synthesis Applicability of ACM for automatic
SoC synthesis Tools for DSE with the semantics
introduced in ACM.
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Thanks
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Clarifications
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Comparison between TSS SystemC
Performance Comparison
SystemC is slower
SystemC is faster
In Worst case SystemC is slower than TSS by 3
times