CPE 626 The SystemC Language

1
CPE 626 The SystemC Language

• Aleksandar Milenkovic
• E-mail milenka_at_ece.uah.edu
• Web http//www.ece.uah.edu/milenka

2
Outline

• Introduction
• Data Types
• Modeling Combinational Logic
• Modeling Synchronous Logic
• Misc

3
Introduction

• What is SystemC?
• Why SystemC?
• Design Methodology
• Capabilities
• SystemC RTL

4
What is SystemC

• An extension of C enabling modeling of
  hardware descriptions
• SystemC adds a class library to C
• Mechanisms to model system architecture
• Concurrency multiple processes executed
  concurently
• Timed events
• Reactive behavior
• Constructs to describe hardware
• Signals
• Modules
• Ports
• Processes
• Simulation kernel

5
What is SystemC

• Provides methodology for describing
• System level design
• Software algorithms
• Hardware architecture
• Design Flow
• Create a system level model
• Explore various algorithms
• Simulate to validate model and optimize design
• Create executable specifications
• Hardware team and software team use the same
  specification

Test input files
6
C/SystemC Development Environment
SystemC Class Library and Simulation Kernel
Compiler Linker Debugger
Source files in SystemC (design testbenches)
Make
Simulatorexecutable
Run
Test, log output files
Test input files
7
Why SystemC?

• Designs become
• Bigger in size
• Faster in speed
• Larger in complexity
• Design description on higher levels of
  abstraction enables
• Faster simulation
• Hardware/software co-simulation
• Architectural Exploration

Fastest
System
Iteration Time
RTL
Chip
Slowest
8
Why SystemC?

• SystemC describes overall system
• System level design
• Describing hardware architectures
• Describing software algorithms
• Verification
• IP exchange

9
Non-SystemC Design Methodology
System Designer
RTL Designer
Hand-over
Understand specification
Write conceptualC/C model
Partition design
Verify against specification
Write each blockin HDL
Write testbench
Reverify
Write testbenches
Synthesize
To implementation
10
SystemC Design Methodology
System Designer
RTL Designer
Hand-over
Understand specification
Write conceptualC/C model
Partition design
Verify against specification
Refine SystemCmodel to RTL
Write testbench
Reverify
Reuse testbench
Synthesize
To implementation
11
System Level Design Process

• Not synthesizable
• Event driven
• Abstract data types
• Abstract communication
• Untimed

System Level model
Explore algorithms Verify against specifications
Refine
Timed model
Explore architectures Do performance analysis

• Event driven

Partition hardware / software

• Synthesizable
• Algorithmic description
• I/O cycle accurate
• Clocked

Hardware
Software
RTOS
Behavioral model
Refine

• Synthesizable
• - FSM
• Clocked

Target code
RTL model
12
SystemC Capabilities

• Modules
• SC_MODULE class
• Processes
• SC_METHOD, SC_THREAD
• Ports input, output, inout
• Signals
• resolved, unresolved
• updates after a delta delay
• Rich set of data types
• 2-value, 4-value logic
• fixed, arbitrary size
• Clocks
• built-in notion of clocks

• Event-base simulation
• Multiple abstraction levels
• Communication protocols
• Debugging support
• Waveform tracing
• VCD Value Change Dump (IEEE Std. 1364)
• WIF Waveform Interch. F.
• ISDB Integrated Signal Data Base
• RTL synthesis flow
• System and RTL modeling
• Software and Hardware

13
SystemC Half Adder
// File half_adder.h include systemc.h SC_MODU
LE(half_adder) sc_inltboolgt a,
b sc_outltboolgt sum, carry void
prc_half_adder() SC_CTOR(half_adder)
SC_METHOD(prc_half_adder) sensitive ltlt a
ltlt b
// File half_adder.cpp include
half_adder.h void half_adderprc_half_adder()
sum a b carry a b
14
SystemC Decoder 2/4
// File decoder2by4.h include systemc.h SC_MOD
ULE(decoder2by4) sc_inltboolgt
enable sc_inltsc_uintlt2gt gt select sc_outltsc_uin
tlt4gt gt z void prc_decoder2by4() SC_CTOR(deco
der2by4) SC_METHOD(prc_half_adder) sensitiv
e(enable, select)
// File decoder2by4.cpp include
decoder2by4.h void decoder2by4prc_
decoder2by4() if (enable) switch(select.rea
d()) case 0 z0xE break case 1 z0xD
break case 2 z0xB break case 3 z0x7
break else z0xF
Note Stream vs. Function notation
sensitive ltlt a ltlt b // Stream notation
style sensitive(a, b) // Function notation style
15
Hierarchy Building a full adder
// a destructor full_adder() delete
ha1_ptr delete ha2_ptr
// File full_adder.h include systemc.h SC_MODU
LE(full_adder) sc_inltboolgt a,b,carry_in sc_o
utltboolgt sum,carry_out sc_signalltboolgt c1, s1,
c2 void prc_or() half_adder ha1_ptr,
ha2_ptr SC_CTOR(full_adder) ha1_ptr new
half_adder(ha1) ha1_ptr-gta(a)
ha1_ptr-gtb(b) ha1_ptr-gtsum(s1) ha1_ptr-gtcarr
y(c1) ha2_ptr new half_adder(ha2) (ha2_
ptr)(s1, carry_in,sum,c2) SC_METHOD(prc_or)
sensitive ltlt c1 ltlt c2
// File full_adder.cpp include
full_adder.h void full_adderprc_or() carry_
out c1 c2
16
Verifying the Functionality Driver
// File driver.h include systemc.h SC_MODULE(d
river) sc_outltboolgt d_a,d_b,d_cin void
prc_driver() SC_CTOR(driver)
SC_THREAD(prc_driver)
// File driver.cpp include driver.h void
driverprc_driver() sc_uintlt3gt
pattern pattern0 while(1)
d_apattern0 d_bpattern1 d_cinpatt
ern2 wait(5, SC_NS) pattern
17
Verifying the Functionality Monitor
// File monitor.h include systemc.h SC_MODULE(
monitor) sc_inltboolgt m_a,m_b,m_cin, m_sum,
m_cout void prc_monitor()
SC_CTOR(monitor) SC_THREAD(prc_monitor) s
ensitive ltlt m_a,m_b,m_cin, m_sum,
m_cout
// File monitor.cpp include monitor.h void
monitorprc_monitor() cout ltlt At time ltlt
sc_time_stamp() ltlt cout
ltlt(a,b,carry_in) cout ltlt m_a ltlt m_b ltlt
m_cin cout ltlt (sum,carry_out) cout ltlt
m_sum ltlt m_cout ltlt endl
18
Verifying the Functionality Main
// File full_adder_main.cpp include
driver.h include monitor.h include
full_adder.h int sc_main(int argc, char
argv) sc_signalltboolgt t_a, t_b, t_cin,
t_sum, t_cout full_adder f1(FullAdderWithHalf
Adders) f1 ltlt t_a ltlt t_b ltlt t_cin ltlt t_sum ltlt
t_cout driver d1(GenWaveforms) d1.d_a(t_a)
d1.d_b(t_b) d1.d_cin(t_cin) monitor
m1(MonitorWaveforms) m1 ltlt t_a ltlt t_b ltlt
t_cin ltlt t_sum ltlt t_cout sc_start(100,
SC_NS) return(0)
19
Modeling Combinational Logic
// File bist_cell.h include systemc.h SC_MODUL
E(bist_cell) sc_inltboolgt b0,b1,d0,d1 sc_outltb
oolgt z void prc_bist_cell() SC_CTOR(bist_cell)
SC_METHOD(prc_bist_cell) sensitive
ltltb0ltltb1ltltd0ltltd1
// File bist_cell.cpp include
bist_cell.h void bist_cellprc_bist_cell() b
ool s1, s2, s3 s1 !(b0d1) s2
!(d0b1) s3 !(s2s1) s2 s2s1 z
!(s2s3)
// File bist_cell.cpp include
bist_cell.h void bist_cellprc_bist_cell()
z !(!(d0b1)!(b0d1))! (!(d0b1)!(b0d1)))

• Use SC_METHOD process with an event sensitivity
  list

20
Modeling Combinational Logic Local Variables
// File bist_cell.cpp include
bist_cell.h void bist_cellprc_bist_cell() b
ool s1, s2, s3 s1 !(b0d1) s2
!(d0b1) s3 !(s2s1) s2 s2s1 z
!(s2s3)
// File bist_cell.cpp include
bist_cell.h void bist_cellprc_bist_cell()
z !(!(d0b1)!(b0d1))! !(d0b1)!(b0d1)))

• Local variables in the process (s1, s2, s3)do
  not synthesize to wires
• Hold temporary values (improve readability)
• Are assigned values instantaneously (no delta
  delay) one variable can represent many wires
  (s2)
• signals and ports are updated after a delta
  delay
• Simulation is likely faster with local variables

21
Modeling Combinational Logic Reading and
Writing Ports and Signals
// File xor_gates.h include systemc.h SC_MODUL
E(xor_gates) sc_inltsc_uintlt4gt gt bre,
sty sc_out ltsc_uintlt4gt gt tap void
prc_xor_gates() SC_CTOR(xor_gates)
SC_METHOD(prc_xor_gates) sensitive ltlt bre
ltlt sty

• Use read() and write() methodsfor reading and
  writing valuesfrom and to a port or signal

// File xor_gates.cpp include
xor_gates.h void bist_cellprc_xor_gates()
tap bre sty
// File xor_gates.cpp include
xor_gates.h void bist_cellprc_xor_gates()
tap bre.read() sty.read()
22
Modeling Combinational Logic Logical Operators
// File xor_gates.h include systemc.h const
int SIZE4 SC_MODULE(xor_gates)
sc_inltsc_uintltSIZEgt gt bre, sty sc_out
ltsc_uintltSIZEgt gt tap void prc_xor_gates() SC_C
TOR(xor_gates) SC_METHOD(prc_xor_gates) sen
sitive ltlt bre ltlt sty

• - xor
• - and
• - or

// File xor_gates.cpp include
xor_gates.h void bist_cellprc_xor_gates()
tap bre.read() sty.read()
23
Modeling Combinational Logic Arithmetic
Operations
sc_uintlt4gt write_addr sc_intlt5gt
read_addr read_addr write_addr read_addr

• Note all fixed precision integer type
  calculations occur on a 64-bit representation
  and appropriate truncation occursdepending on
  the target result size
• E.g.
• write_addr is zero-extended to 64-bit
• read_addr is sign-extended to 64-bit
• is performed on 64-bit data
• result is truncated to 5-bit result and assigned
  back to read_addr

24
Modeling Combinational Logic Unsigned Arithmetic
// File u_adder.h include systemc.h SC_MODULE
(u_adder) sc_inltsc_uintlt4gt gt a, b sc_out
ltsc_uintlt5gt gt sum void prc_u_adder() SC_CTOR(u
_adder) SC_METHOD(prc_u_adder) sensitive
ltlt a ltlt b
// File u_adder.cpp include u_adder.h void
u_adder prc_s_adder() sum a.read()
b.read()
25
Modeling Combinational Logic Signed Arithmetic
// File s_adder.h include systemc.h SC_MODULE
(s_adder) sc_inltsc_intlt4gt gt a, b sc_out
ltsc_intlt5gt gt sum void prc_s_adder() SC_CTO
R(s_adder) SC_METHOD(prc_s_adder) sensitive
ltlt a ltlt b
// File s_adder.cpp include s_adder.h void
s_adder prc_s_adder() sum a.read()
b.read()
26
Modeling Combinational Logic Signed Arithmetic
(2)
// File s_adder.cpp include s_adder_c.h void
s_adder_cprc_ s_adder_c() sc_intlt5gt
temp temp a.read() b.read() sum
temp.range(3,0) carry_out temp4
// File s_adder_c.h include systemc.h SC_MODU
LE(s_adder_c) sc_inltsc_intlt4gt gt a, b sc_out
ltsc_intlt4gt gt sum sc_out ltboolgt
carry_out void prc_s_adder_c() SC_CTOR(s_a
dder_c) SC_METHOD(prc_s_adder_c) sensitive
ltlt a ltlt b
27
Modeling Combinational Logic Relational
Operators
// File gt.h include systemc.h const
WIDTH8 SC_MODULE(gt) sc_inltsc_intlt4gt gt a,
b sc_out ltboolgt z void prc_gt() SC_CTOR(gt)
SC_METHOD(prc_gt) sensitive ltlt a ltlt
b
// File gt.cpp include gt.h void
gtprc_gt() sc_intltWIDTHgt atemp, btemp
atemp a.read() btemp b.read() z
sc_uintltWIDTHgt(atemp.range(WIDTH/2-1,0)) gt
sc_uintltWIDTHgt(btemp.range(WIDTH-1,WIDTH/2))
28
Modeling Combinational Logic Vector and Ranges
// Bit or range select of a port // or a signal
is not allowed sc_inltsc_uintlt4gt gt
data sc_signalltsc_bvlt6gt gt counter sc_uintlt4gt
temp sc_uintlt6gt cnt_temp bool mode,
preset mode data2 // not allowed
//instead temp data.read() mode
temp2 counter4 preset // not
allowed cnt_temp counter cnt_temp4
preset counter cnt_temp
29
Multiple Processes and Delta Delay
// File mult_proc.h include systemc.h SC_MODU
LE(mult_proc) sc_inltboolgt in sc_outltboolgt
out sc_signalltboolgt c1, c2 void
mult_proc1() void mult_proc2() void
mult_proc3() SC_CTOR(mult_proc)
SC_METHOD(mult_proc1) sensitive ltlt
in SC_METHOD(mult_proc2) sensitive ltlt
c1 SC_METHOD(mult_proc3) sensitive ltlt
c2
// File mult_proc.cpp include
mult_proc.h void mult_procmult_proc1() c1
!in void mult_procmult_proc2() c2
!c1 void mult_procmult_proc3() out
!c2
30
If Statement
// File simple_alu.h include systemc.h const
int WS4 SC_MODULE(simple_alu)
sc_inltsc_uintltWSgt gt a, b sc_inltboolgt
ctrl sc_outlt sc_uintltWSgt gt z void
prc_simple_alu() SC_CTOR(simple_alu)
SC_METHOD(prc_simple_alu) sensitive ltlt a
ltlt b ltlt ctrl
// File simple_alu.cpp include
simple_alu.h void simple_aluprc_simple_alu()
if(ctrl) z a.read() b.read() else z
a.read() b.read()
31
If Statement Priority encoder
// File priority.h include systemc.h const
int IS4 const int OS3 SC_MODULE(priority)
sc_inltsc_uintltISgt gt sel sc_outlt sc_uintltOSgt
gt z void prc_priority() SC_CTOR(priority)
SC_METHOD(prc_priority) sensitive ltlt
sel
// File priority.cpp include priority.h void
priorityprc_priority() sc_uintltISgt
tsel tsel sel.read() if(tsel0) z
0 else if (tsel1) z 1 else if (tsel2) z
2 else if (tsel3) z 3 else z 7
32
Switch Statement ALU
// File alu.cpp include alu.h void
priorityprc_alu() sc_uintltWORDgt ta, tb ta
a.read() tb b.read() switch (op) case
add z tatb break case sub z tatb
break case mul z tatb break case div
z ta/tb break
// File alu.h include systemc.h const int
WORD4 enum op_type add, sub, mul,
div SC_MODULE(alu) sc_inltsc_uintltWORDgt gt a,
b sc_inltop_typegt op sc_outlt sc_uintltWORDgt gt
z void prc_alu() SC_CTOR(alu)
SC_METHOD(prc_alu) sensitive ltlt a ltlt b ltlt
op
33
Loops

• C loops for, do-while, while
• SystemC RTL supports only for loops
• For loop iteration must be a compile time
  constant

34
Loops An Example
// File demux.cpp include demux.h void
priorityprc_demux() sc_uintlt3gt
j sc_uintltOWgt temp for(j0 jltOW j)
if(aj) tempj 1 else tempj 0
// File demux.h include systemc.h const int
IW2 const int OW4 SC_MODULE(demux)
sc_inltsc_uintltIWgt gt a sc_outltsc_uintltOWgt gt
z void prc_demux() SC_CTOR(demux)
SC_METHOD(prc_demux) sensitive ltlt a
35
Methods

• Methods other than SC_METHOD processes can be
  used in a SystemC RTL

36
Methods
// File odd1s.cpp include odd1s.h void
odd1sprc_odd1s() is_odd isOdd(data_in) b
ool odd1sisOdd(sc_uintltSIZEgt abus) bool
result int i for(i0 iltSIZE i) result
result abusi return(result)
// File odd1s.h include systemc.h const int
SIZE 6 SC_MODULE(odd1s) sc_inltsc_uintltSIZEgt
gt data_in sc_outltboolgt is_odd bool
isOdd(sc_uintltSIZEgt abus) void
prc_odd1s() SC_CTOR(odd1s) SC_METHOD(prc_od
d1s) sensitive ltlt data_in
37
Modeling Synchronous Logic Flip-flops
// File dff.cpp include dff.h void
dffprc_dff() q d
// File dff.h include systemc.h SC_MODULE(dff
) sc_inltboolgt d, clk sc_outltboolgt q void
prc_dff() SC_CTOR(dff) SC_METHOD(prc_dff)
sensitive_pos ltlt clk
38
Registers
// File reg.h include systemc.h const int
WIDTH 4 SC_MODULE(reg) sc_inltsc_uintltWIDTHgt
gt cstate sc_inltboolgt clock sc_outlt
sc_uintltWIDTHgt gt nstate void
prc_reg() SC_CTOR(dff) SC_METHOD(prc_dff)
sensitive_neg ltlt clock
// File reg.cpp include reg.h void
regprc_reg() cstate nstate
39
Sequence Detector 101
// File sdet.h include systemc.h SC_MODULE(sd
et) sc_inltboolgt clk, data sc_outltboolgt
sfound sc_signalltboolgt first, second,
third // synchronous logic process void
prc_sdet() // comb logic process void
prc_out() SC_CTOR(sdet) SC_METHOD(prc_sdet)
sensitive_pos ltlt clk SC_METHOD(prc_out)
sensitive ltlt first ltlt second ltlt third
// File sdet.cpp include sdet.h void
sdetprc_sdet() first data second
first third second void sdetprc_out()
sfound first (!second) third
40
Counter Up-down, Async Negative Clear
// File cnt4.h include systemc.h const int
CSIZE 4 SC_MODULE(sdet) sc_inltboolgt mclk,
cl, updown sc_outltsc_uintltCSIZEgt gt dout void
prc_cnt4() SC_CTOR(cnt4) SC_METHOD(prc_cnt4
) sensitive_pos ltlt mclk sensitive_neg ltlt
cl
// File cnt4.cpp include cnt4.h void
sdetprc_cnt4() if(!clear) data_out
0 else if(updown) doutdout.read()1 e
lse doutdout.read()-1
41
Latches
// File latch.cpp include latch.h void
latchprc_latch() if(en) q d
// File latch.h include systemc.h SC_MODULE(l
atch) sc_inltboolgt d, en sc_outltboolgt
q void prc_latch() SC_CTOR(latch)
SC_METHOD(prc_latch) sensitive ltlt en ltlt
d
42
Avoiding latches
// File su.cpp include su.h void
suprc_su() switch (cs) case s0 case
s3 z 0 break case s1 z 3 break
default z 1 break
// File su.cpp include su.h void
suprc_su() z 1 switch (cs) case s0
case s3 z 0 break case s1 z 3
break
43
Tri-state drivers
// File tris.h include systemc.h SC_MODULE(tr
is) sc_inltboolgt rdy, dina, dinb sc_outltboolgt
out void prc_tris() SC_CTOR(tris)
SC_METHOD(prc_tris) sensitive ltlt dina ltlt
dinb ltlt rdy
// File tris.cpp include tris.h void
trisprc_tris() if(rdy) out
sc_logic(Z) else out sc_logic(dina.read()
dinb.read())
44
More on latches
// File su.cpp include su.h void
suprc_su() switch (cs) case s0 case
s3 z 0 break case s1 z 3 break
// File su.h include systemc.h enum states
s0,s1,s2,s3 const int ZS 2 SC_MODULE(su)
sc_inltstatesgt cs sc_outltsc_uintltZSgt gt
z void prc_su() SC_CTOR(su)
SC_METHOD(prc_su) sensitive ltlt cs
When cs has value s2 port z is not assigned a
value gt to model the behavior of the process a
latch is inferred for port z.
45
Modeling an FSM

• Moore Machine Outputs depend only on the
  present state

Combinational Network
Next State (Q)
Inputs(X)
State(Q)
State Register
Combinational Network
Clock
46
Modeling an FSM

• Mealy Machine Outputs depend on both the
  present state and inputs

Combinational Network
Next State (Q)
Inputs(X)
State(Q)
State Register
Combinational Network
Clock
47
Moore FSM
a
s1
s0
!a
!a
a
z0
z1
s2
a
a
s3
!a
z0
!a
z1
48
Modeling an FSM Moore Machine
// File moore.h include systemc.h SC_MODULE(mo
ore) sc_inltboolgt a, clk, reset sc_outltboolgt
z enum states s0,s1,s2,s3 sc_signalltstatesgt
mstate void prc_moore() SC_CTOR(moore)
SC_METHOD(prc_moore) sensitive_pos ltlt
clk
49
Modeling an FSM Moore Machine
// File moore.cpp include moore.h void
mooreprc_moore() if(reset) mstate
s0 else switch (mstate) case s0 z 1
mstate a ? s0 s2 break case s1 z 0
mstate a ? s0 s2 break case s2 z 0
mstate a ? s2 s3 break case s3 z 0
mstate a ? s1 s3 break
When synthesized, how many DFF we have?
50
Modeling an FSM Moore Machine
// File moore2.h include systemc.h SC_MODULE(m
oore2) sc_inltboolgt a, clk, reset sc_outltboolgt
z enum states s0,s1,s2,s3 sc_signalltstates
gt mstate void prc_states() void
prc_outputs() SC_CTOR(moore2)
SC_METHOD(prc_states) sensitive_pos ltlt
clk SC_METHOD(prc_outputs) sensitive ltlt
mstate
51
Modeling an FSM Moore Machine
// File moore2.cpp include moore2.h void
moore2prc_states() if(reset) mstate
s0 else switch (mstate) case s0 mstate
a ? s0 s2 break case s1 mstate a ? s0
s2 break case s2 mstate a ? s2 s3
break case s3 mstate a ? s1 s3
break void moore2prc_outputs() switch(m
state) case s3 case s0 z 1
break case s1 case s2 z 0 break
52
Writing Test-benches

• Typical test-bench structure

monitor.cpp
stimulus.cpp
dut.cpp
monitor.h
stimulus.h
dut.h
main.cpp
53
SystemC Simulation Control

• sc_clock generate clock signal
• sc_trace dump trace information into a file in
  the specified format
• sc_start run simulation for specified time
• sc_stop stop simulation
• sc_time_stamp get current simulation time with
  time units
• sc_simulation_time get current simulation time
  without time units
• sc_cycle, sc_initialize use to perform
  cycle-level simulation
• sc_time specify a time value

54
Sc_clock
// on-off period of 10ns, duty cycle 50, initial
value is 1 sc_clock rclk(rclk, 10, SC_NS) //
10 ns period, duty is 20, // first edge occurs
at 5ns, initial value is 0 sc_clock mclk(mclk,
10, SC_NS, 0.2, 5, SC_NS, false)
Draw waveforms for rclk and mclk!
55
Sc_trace

• Formats supported
• VCD Value Change Dumped
• WIF Waveform Interchange Format
• ISDB Integrated Signal Data Base

// open a file file myvcddump.vcd will be
created sc_trace_file tfile sc_create_vcd_trace
_file(myvcddump) // in general
sc_create_vcdwifisdb_trace_file // specify
signals whose values you want to be
saved sc_trace(tfile, signal_name,
signal_name) // close file sc_close_vcd_trace_
file(pointer_to_trace_file)
56
Sc_start, sc_stop

• Tells the simulation kernel to start simulation
• Stop simulation

// run simulation for 100ms sc_start(100,
SC_MS) // run simulator forever sc_start(-1)
sc_stop()
57
Sc_time_stamp, sc_simulation_time

• Returns current simulation time
• Returns an integer value of type double

// run simulation for 100ms cout ltlt Current time
is ltlt sc_time_stamp() ltlt endl
double curr_time sc_simulation_time()
58
sc_cycle, sc_initialize
// initialize simulation kernel
sc_initialize() // sc_cycle executes all the
processes that are ready to run// until no more
processes are ready to run // then, traces the
signals and advances the simulation// by the
specified amount of time sc_cycle(10, SC_US) //
10 microseconds
59
sc_time
// specify a time value sc_time t1 (100,
SC_NS) sc_time t2 (20, SC_PS) sc_start(t1) //
run simulation for 100ns sc_start(100,
SC_NS) sc_cycle(t2) sc_set_time_resolution(10
0, SC_PS)
60
Creating waveforms
// file wave.cpp include wave.h void
waveprc_wave() sig_out 0 wait(5,
SC_NS) sig_out 1 wait(2, SC_NS) sig_out
0 wait(5, SC_NS) sig_out 1 wait(8,
SC_NS) sig_out 0
// file wave.h include systemc.h SC_MODULE(wav
e) sc_outltboolgt sig_out void
prc_wave() SC_CTOR(wave) SC_THREAD(prc_wav
e)