Design for Verification of SystemC Transaction Level Models

1
Design for Verification of SystemC Transaction
Level Models

• Habibi, A. Tahar, S.
• Design, Automation and Test in Europe, 2005.
  Proceedings2005 Page(s)560 - 565 Vol. 1
• Presenter HYChen

2
Abstract

• Transaction level modeling allows exploring
  several SoC design architectures leading to
  better performance and easier verification of the
  final product. In this paper, we present an
  approach to design and verify SystemC models at
  the transaction level. We integrate the
  verification as part of the design-flow. In the
  proposed approach, we first model both the design
  and the properties (written in PSL) in UML. Then,
  we translate them into an intermediate format
  modeled with Abstract State Machines (ASM). The
  ASM model is used to generate an FSM of the
  design including the properties. Checking the
  correctness of the properties is performed
  on-the-fly while generating the state machine.
  Finally, we translate the verified design to
  SystemC and map the properties to a set of
  assertions (as monitors in C) that can be
  re-used to validate the design at lower levels
  through simulation. We illustrate our approach on
  two case studies including the PCI bus standard
  and a generic Master/Slave architecture from the
  SystemC library.

3
Whats the problem?

• the problem of growth in complexity and size of
  systems.
• RTL level
• effort 1) design 2) verify 3) simulation.
• Pin-level
• SystemC
• system level language.
• Transaction level modeling.
• Whats the problem?
• Verification of a SystemC model is a serious
  bottleneck in the design cycle.

4
Design and Verification Flow
5
Property Specification Language(PSL)

• Yet historically, the process of specification
  has consisted of creating a natural language
  description of a set of design requirements. This
  form of specification is both ambiguous and, in
  many cases, unverifiable due to the lack of a
  standard machine-executable representation.
  Furthermore, ensuring that all functional aspects
  of the specification have been adequately
  verified (that is, covered) is problematic.
• Property Specification Language Reference Manual

• always ((a next3(b)) -gt c)

• always (a -gt next3(b))

6
PSL(cont.)

• Boolean layer
• a single evaluation cycle
• Temporal layer
• a series of evaluation cycles
• example
• if signal c is asserted, then signal d shall be
  asserted before signal e is asserted, but no more
  than eight clock cycles later.
• Verification layer
• This layer is used to tell the verification tools
  what to do with the properties described by the
  temporal layer.
• Modeling layer
• This layer is used to model the behavior of
  design inputs

7
Modeling PSL Properties

• First Step
• UML Model (easy transformed to PSL)
• Second Step
• AML Model
• Embedded PSL in ASM Language
• ASM using AsmL Tool

8
Modeling PSL Properties UML Sequence Diagram

• UML sequence diagram to adequate for PSL
  representation
• Clocks
• Number of cycles
• Mtd5 says that the method Mtd is executed for
  exactly 5 consecutive cycles.
• Temporal operators
• always executed (A),
• eventually executed (E),
• Executed Until a condition is fulfilled (U)
• Sequence operations
• includes information about the order of executing
  certain sequences (for e.g., next, prev etc.)
• Text output
• refers to a message that is displayed in case the
  method fails
• Method duration
• certain methods are supposed to execute for a
  certain number of cycles
• an operator to specify such an information

9
Modeling PSL Properties UML Example Diagram
10
Modeling PSL Properties - ASM Model

• Abstract State Machines (ASM)
• BOOK
• Y.Gurevich. Evolving Algebras 1993 Lipari Guide.
  In Specification and Validation Methods, pages
  936. 1995
• a formal specification method for software and
  hardware systems
• supports object-oriented modeling
• comparison to Cand Java.
• all the parameters of PSL properties are defined
  as objects
• AsmL tool (developed by Microsoft) can
  automatically compile code into a C or .NET code
• can be compiled and executed with the concrete
  SystemC level

11
Modeling SystemC

• SystemC
• built on standard C.
• an event-driven simulator.
• It works with events and processes(function).
• ASM Model
• FSM generation algorithm(four input)
• methods
• The transitions in the FSM are the method calls
• actions
• The methods in the model program that appear in
  the transitions are called actions.
• variables
• The states in the FSM are determined by the
  values of selected variables in the model
  program, called state variables.
• domains
• finite collections of values from which method
  arguments are taken

12
Modeling SystemC ASM Example (For FSM)
method
action
13
Modeling SystemC FSM generation algorithm

• a model M
• a set of classes, C c1, . . . , cn
• For every class ci in C, we denote its set of
  methods by and the set of members by
  .

14
Modeling SystemC - Translation to C

• If Verify ASM model Correct
• Translate ASM model to SystemC
• The transformation is purely syntactical

15
Verification Methodology

• verification process
• model checking at the ASM level
• assertion based verification at the C/C level.
• model checking (PSL)

16
Verification Methodology Model Checking

• P S1 OP S2
• gt P always true when (!S1 S2)
• ? P always true when ((S1 S2) (!S1
  !S2))
• every state in the FSM generated by the AsmL tool
• FSM(P) Peval(S1) gt Pvalue(S2)
• respectively, if the property can be evaluated
  and the value of the property in the current
  state
• FSM generation stops when an error is detected.

17
Verification Methodology Assertion Based
Verification

• (1) Updating the SystemC design to interface to
  the assertion.
• (2) Generating the assertion (in C) from its ASM
  description.
• (3) Integrating the assertion in the design.
• Most of the effort is spent in updating the
  SystemC design to get it connected the assertion
  monitor.

18
Experimental Results

• Proposed design and verification methodology
• two models
• PCI Bus standard
• An extension of the Master/Slave Bus structure
  provided by the SystemC distribution

19
Experimental Results - PCI Bus
20
Experimental Results Master/Slave case study

• a shared bus, an arbiter
• Blocking Mode burstmode
• Non-Blocking Mod a single data word.

21
Conclusion

• Presented a methodology to design and verify
  SystemC transactional models
• starting from a UML system specification and
  integrating an intermediate ASM layer
• defined a set of translation rules to transform
  the designs model in ASM to its implementation
  in SystemC.