Lecture 1: Introduction to Microprocessors and Microcomputers

1
Lecture 1 Introduction to Microprocessors and
Microcomputers

• Seungryoul Maeng
• Computer Science, KAIST
• Fall 2000

2
The History of Intels Microprocessors

• Pentium III
• 1999
• Pentium Pro MMX Internet Streaming SIMD
  Instructions
• 0.25 micron, 9.5 million Trs
• 600 MHz, 550 MHz,...
• 32 K(16K/16K) non-blocking level 1 cache

3
IBM PC/AT and ISA Bus
4
Pentium Processor/82430 PCIset ISA
Host Bus
Pentium Processor
CNTL
ADDR
DATA
Latch
82434 PCMC
82433 LBX
DRAM
SRAM
PCI BUS
CNTL
ADDR/DATA
82378 SIO
Graphics
PCI devices
ISA BUS
5
ISA Bus Interface Signals
6
ISA Bus Interface Signals
7
Block Diagram of the System Board
External Master
data
CPU
addr
ISA Bus
Memory
addr
data
DMA
MEM
I/O

• All signal lines are TTL compatible. Fan-out are
  two low power Shottkey(LS) TTLs.
• SA0 through SA19 System Address Bus(I/O)
• to address memory and I/O devices 16MB of memory
  with LA17 through LA23
• input when CPUHLDA is high and MASTER is low
  output at all other times
• SA bus driven by CPU when CPUHLDA is low SA bus
  driven by 8237 DMA controller when CPUHLDA is
  high
• latched with an internally generated ALE signal

8
Lect 2 Real Addressed Mode S/W Architecture of
the 80386DX Microprocessor
9
386DX Microprocessor

• Internal Architecture

10
Real-Mode Software Architecture

• reset -gt real mode object code compatible with
  8086
• Real-mode software model

11
Pointer and GPR

• Instruction Pointer (2.7)
• 16-bit IP in real mode
• next code address CSIP
• General Purpose Data Registers (2.8)

12
Pointer and GPR
13
Pointers and Index Registers (2.9)

• two index registers (ESI, EDI) and two pointer
  registers (EBP, ESP)
• contains offset addresses (16-bit in real mode
  64 KB)
• ESP(extended stack pointer) and EBP(extended base
  pointer)
• combined with the contents of the SS register to
  produce physical memory address
• TOS (top of stack) SSSP
• BP an offset relative to the SS register

14
Flag Register (2.9)

• ESI (extended source index register) and EDI
  (extended destination index register)
• automatically combined with the value in the DS
  register
• FLAGS REGISTER (2.10)
• 32-bit flags just nine of its bits are active in
  the real mode

15
Generating A Real-Mode Memory Addresses (2.11)

• Real-mode physical address generation

16
Example
Segment Base
1 2 3 4
Logical Address
Offset
0 0 2 2
0 0 2 2
1 2 3 6
2
Physical Address
17
Real-Mode Input/Output Address Space (2.13)
18
Lect 3 Instruction Set and Addressing Modes
19
386 Instruction Set (3.4)

• Basic Instruction Set 8086/8088 instruction set
• Extended Instruction Set 80286 several new
  instructions and additional addressing modes
• 80386 specific instruction set

80386
80286
8086/8088
Protected Mode
System control Instruction set
System control Instruction set
Basic Extended 80386 specific Instruction Set
Basic Extended Instruction Set
Basic Instruction Set
Real Mode
20
386 Instruction Set (3.4)

• Addressing Modes of 386DX (3.5)
• Addressing Modes a method of specifying an
  operand
• Operands in REG, Memory, I/O ports, and within
  Instruction
• Control Transfer direct, indirect addressing
• the modes available
• register addressing REG
• immediate addressing within Instruction
• direct addressing
• register indirect addressing
• based addressing
• indexed addressing
• based indexed addressing

MEM or I/O
21
Lect 4 Instruction Encoding and Instruction Set
22
Instruction Encoding
General Instruction Format
23
Encoding the instruction in Machine code

• Example
• MOV BL, AL MOV opcode byte 100010dw
• d 0 REG field is source w 1 for word
  operation mod r/m 11 011 REG 000
• First byte 10001000 (88H) Second byte 11
  000 011 (C3H)
• ADD BXDI1234H, AX ADD opcode byte
  000000dw
• d0 REG field is source w 1 for word
  operation mod r/m 10 001 REG 000
• First byte 00000001 (01H) Second byte 10 000
  001 (81H)
• Resulting Machine code 01813412H

24
80386 Instruction Set

• 80386 base instruction set encoding table See
  Fig 4.5
• Instruction Types
• General Data Transfer
• Arithmetic/Logic
• Shift/Rotate
• Bit test and bit scan
• Flag Control
• Control Transfer
• String handling
• System Control

25
Control Transfer

• Stack Frame Instructions ENTER and LEAVE
• to allocate and deallocate a data area called a
  stack frame
• ENTER make a stack frame
• ENTER imm16,0 Make procedure stack frame
• ENTER imm16,1 Make stack frame for procedure
  parameter
• ENTER imm16,imm8 Make stack frame for procedure
  parameter
• first operand the number of bytes to be
  allocated on the stack for local data storage
• second operand lexical nesting level of the
  routine

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Control Transfer
Data for Proc. C (16 bytes) BP for Proc. C BP
for Proc. B BP for Proc. A BP for Proc. B Ret
addr for proc. B Data for Proc. B (12 bytes) BP
for Proc. B BP for Proc. A BP for Proc. A Ret
addr for proc. A Data for Proc. A (32 bytes) BP
for Proc. A Old BP
Stack frame for C
BP when executing Procedure C
Stack frame for B
BP when executing Procedure B
Stack frame for A
BP when executing Procedure A
27
String Handling

• Loop and Loop-handling Instructions
• LOOP, LOOPE/Z, LOOPNE/NZ CX must be preloaded
  with a count
• String and String-Handling Instructions
• MOVSB/W/D, compare string, scan string, load
  string, store string
• the contents of both SI and DI are automatically
  incremented or decremented.
• REP repeat string
• Check Array Index Against Bounds
• BOUND r16, m1616 check if r16 is within bounds
• BOUND r32, m32m32 check if r32 is within bounds
• operation if (LeftSRC lt RightSRC or LeftSRCgt
  RightSRCOperandSize/8)
• then Interrupt 5

28
Lect 5 Protected-Mode Software Architecture
29
Protected-Mode Register Model

• GDTR global descriptor table
• LDTR local descriptor table
• IDTR interrupt descriptor table
• TR task register
• EIP 32 bits in length
• EFLAGS
• CR0, CR1, CR2, CR3
• DR0-DR7(Debug registers)
• TR6-TR7(Test registers)

EIP
CS DS SS ES FS GS
AX BX CX DX
SP BP SI DI
DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7
EFLAGS
0
47
15
16
Limit
Base
GDTR IDTR LDTR
Base
Limit
MSW
CR0 CR1 CR2 CR3
TR6 TR7
TR
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Segment Descriptors

• Descriptor
• the element by which the on-chip memory manager
  hardware manages the segmentation of the
  80386DXs 64T-byte virtual memory address space.
• One descriptor exists for each segment of memory
  in virtual address space.
• 8 bytes long and contains three kinds of
  information
• Limit
• Base
• Access Rights
• Types of segment descriptors
• system segment descriptor(s0), non-system
  segment descriptor(s1)(code and data)

31
Segment Descriptors
23
16
15
8
7
0
32
24
AVL
4
BASE 31..24
G
X
0
P
DPL
S
TYPE
A
BASE 23..16
LIMIT 19..16
7
SEGMENT LIMIT 15 .. 0
3
SEGMENT BASE 15 .. 0
0
32
Global Descriptor Table

• Global Descriptor Table
• GDT provides a mechanism for defining the
  characteristics of the 386 global memory address
  space. Global memory is a general system resource
  that is shared by many or all software tasks.
• contains system segment descriptors

8191
Global Descriptor Table (GDT)
Global Descriptor Table Register(GDTR)
MAX 64k bytes 8K entries
16
15
47
0
LIMIT
BASE
1
0
33
Interrupt Descriptor Table

• Interrupt Descriptor Table (IDT)
• contains interrupt descriptors, not segment
  descriptors
• IDT can also be up to 64KB But 386 only supports
  up to 256 interrupts and exceptions(2KB)

255
Interrupt Descriptor Table (IDT)
Interrupt Descriptor Table Register(IDTR)
MAX 2k bytes 256 entries
16
47
15
0
LIMIT
BASE
1
0
34
Local Descriptor Table

• Local Descriptor Table
• Each task can have access to own private
  descriptor table(LDT) in addition to GDT.
• contains descriptors that provide access to code
  and data in segments of memory

15
0
GDT
GDTR
LIMIT
31
BASE
15
0
LDTR

selector
LDT0
LDTR cache
0
15
LIMIT
31
BASE
program invisible

LDTn
35
Control Registers
MP math present EM emulate R extension
type TS task switched

• MSW CR0
• the lower 5 bits of CR0 are system-control flags
• PE protected-mode enable bit
• At reset, PE is cleared.(real mode)
• Set PE to 1 to enter protected mode
• Once in protected mode, 386 cannot be switched
  back to real mode under SW control

36
Register With Changed Functionality
SEGMENT SELECTOR REGISTER
T I
RPL
INDEX
Requested Privilege Level(RPL)
Indicates selector privilege level desired
1-0
TI0 use global descriptor table (GDT) TI1 use
local descriptor table (LDT)
Table Indicator (TI)
2
15-3
Index
select descriptor entry in table

• Example CS 1007H, GDT base 00100000H, LDT base
  00120000H
• (CS) 0001 0000 0000 0111 RPL 3, TI 1,
  Index 0001 0000 0000 0
• Address of the segment descriptor 00120000H
  1000H 00121000H

37
Protected Memory Management and Address
Translation

• Virtual Address and Virtual Address Space
• virtual address selector(16-bit)
  offset(32-bit)
• 214(16,384 16K) unique segments of memory, each
  of which has a maximum size of 4G bytes
• Total virtual address space 246 , 64 TB

0
47
32
31
offset
selector
T I
RPL
INDEX
38
Physical Address Space and Virtual-to-Physical
Address Translation
SELECTOR
OFFSET
LOGICAL ADDRESS
SEGMENT TRANSLATION
PG?
PAGING DISABLED
PAGING ENABLED
0
31
DIR PAGE
OFFSET
LINEAR ADDRESS
PAGE TRANSLATION
PHYSICAL ADDRESS
39
Segmentation Virtual to Physical Address
Translation
OFFSET
SELECTOR
LOGICAL ADDRESS
Selector Offset(EBX)
(DS)
SEGMENT TRANSLATION
Data Segment
PG?
PAGING DISABLED
Operand
PAGING ENABLED
0
31
DIR PAGE OFFSET
LINEAR ADDRESS
PAGE TRANSLATION
Data Segment Descriptor Cache Register
LDT
Segment Descriptor
PHYSICAL ADDRESS
40
Segment Selector Register and the Cache Registers
Transparently Loaded by MPU
Programmer accessible Selectors
Access Rights
Base Address
Limit
CS

DS
64-bit Segment Descriptor Cache Registers
SS
ES
FS
GS
0
19
20
51
52
63