Input Capture

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Input Capture Output Compare

• Input event detection
• Output event generation
• Pulse-rate sensing
• Pulse-rate modulation
• Pulse-width modulation

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Time Processor Unit (TPU)
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TPU
Controls 16 channels (available as pins). Can
observe events on these channels (input). Can
generate events on these channels (output).
Events transitions to indicate some state.
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TPU
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TPU Timers
Two timers TCR1 TCR2 -- 16 bits each
All channel events are created or captured w.r.t.
a timer.
TCR1 programmed in TPUMCR.
TCR2 can be driven by an external clock.
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TPU Registers
TPU Module Configuration Register TPUMCR 0x30
4000
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TPU Control Registers
TPU Interrupt Configuration Register (TICR) 0x30
4008
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TPU Control Registers
Channel Interrupt Enable Register (CIER) 0x30 400a
0 interrupt disabled 1 interrupt enabled
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TPU Control Registers
Channel Interrupt Status Register (CISR) 0x30 4020
Channel interrupt status 0 interrupt not
asserted 1 interrupt asserted
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Channel Programming
16 predefined functions.
Input Capture capture one or multiple
transitions on an input pin.
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Channel Programming
Program as an output channel. Output Compare
generate an event on the output a single output
transition, a single pulse, or a continuous 50
duty cycle pulse train.
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Channel Initialization
Choose channel function Code for IC 0xA Channel
function code for OC 0x4
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Input Capture Parameters
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Input Capture/Transition Counter
Input Parameters MAX_COUNT The TPU raises an
interrupt after counting as many events as
MAX_COUNT.
Output Parameters TRANS_COUNT current count of
captured transitions. FINAL_TRANS_TIME Timer
time when the final transition (MAX_COUNTth) is
captured. LAST_TRANS_TIME Timer time when the
last transition (TRANS_COUNTth) is captured.
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Memory Map of Parameters
Channel 0 MAX_COUNT 0x30 4104 TRANS_COUNT 0x30
4106 FINAL_TRANS_TIME 0x30 4108 LAST_TRANS_TIME
0x30 410A
General Channel Y MAX_COUNT 0x30
41Y4 TRANS_COUNT 0x30 41Y6 FINAL_TRANS_TIME
0x30 41Y8 LAST_TRANS_TIME 0x30 41YA
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General Parameter Memory Map
0x3041
Ch 0
Ch 1
Ch 2
Ch 15
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Channel Control Options
Part of channel initialization
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Channel Priority
Choose channel priority 0disable 1low
2 medium 3 high
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Channel Function Activation
After initializing channel, the channel function
is activated by host service request, which can
be further specialized through host sequence.
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Host Sequence
Transition sequencing x0 single shot x1
continual
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Typical Initialization Sequence

• Disable the channel before programming it
• CPRch ? 00 (channel priority disabled)
• Assign the channel function
• CFSRch ? 0xA (for input capture/ITC)
• Program the function parameters
• MAX_COUNT1 for input capture
• Channel control TBS 000x (input channel
  capture TCR1) PAC 001 (detect rising edge)
  PSC 11 (do not force)
• Host sequence single shot. Write 00 into
  HSQRRch.
• etc.
• Initialize host service (activate the channel)
• HSRRch ? 01 (initialize TCR mode)
• Enable the channel
• CPRch ? 01, 10, 11

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Shared Register Modification
00 Host service complete ? by TPU channel 01
Initialize TCR mode ? by CPU Program
Modification of HSRR involves read-modify-write
lhz r6, 0x401a(r5) //read andi r6, r6, 0xfffc
// modify (write 01 to HSRRch0) ori r6, r6,
0x1 sh r6, 0x401a(r5) // write
Does it work?
How many independent potential writers into HSRR1?
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Shared Register Modification
We dont really know what happens to ch 1-7
fields while we modify ch 0 field.
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Shared Register Modification.
Solution into ch 1-7 fields, write something we
are definitely not supposed to write.
00 is written by only the TPU, no CPU program
should legitimately write that value.
li r6, 0x1 //00 00 00 00 00 00 01 sth r6,
0x401a(r5)
01
Write guard logic only allows 01, 10, 11 to go
through!
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Output Compare (OC)
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Output Compare (OC)
OC parameters specified by the CPU program
REF_TIME1 as a pointer into the parameter space
of any of the 16 channels. Parameter address
space 0x3041 00 0x3041 fe Need to specify
only 8-bits of address for REF_ADDR1. OFFSET a
16-bit quantity 0x0 0x8000.
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OC Programming
Point REF_ADDR1 to 0x3041 ec (TCR1 value
captured at this parameter address).
OFFSET 0x1000 with TCR1 resolution at 1
micro-s 4.096 milli-s.
Channel function code for OC 0x4 CFSRch ? 0x4
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Output Compare
OC initialization (host service request of 01 --
host initiated pulse mode) writes the current
value TCR1 ? 0x3041 ec TCR2 ? 0x3041ee
Program channel 0 for this pulse.
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OC Channel Control Options
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OC Channel Control
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OC Channel Control
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Other OC Parameters
We will write 0s into RATIO, REF_ADDR2, and
REF_ADDR3.
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OC Output Parameters
When a channel is initialized for OC through a
service request of 01, REF_TIME is computed as
(REF_ADDR1) OFFSET and placed in parameter
REF_TIME. REF_TIME is the next time instant when
an event would occur (and an interrupt is
raised). This is the match event compare TCR1/2
with REF_TIME for a match.
ACTUAL_MATCH_TIME is updated with the TCR1/2
time when the match is serviced (by raising an
interrupt, and changing the level of the output
channel).