Tests carried on detector with FEE

1
Outline

• Tests carried on detector with FEE
• Results of the tests and problems faced
• Possible reasons and investigations
• Proposed solution for saving the boards
• Conclusions.

2
Honeycomb chamber description

• Each PMD Honeycomb chamber consists of a copper
  cathode made of an array of small (5mm) hexagonal
  cells sand-witched between two printed circuit
  boards. Along the axis of each cell, a 20 micron
  gold plated tungsten wire is stretched and
  soldered through the corresponding holes on the
  PCBs.
• Connections to the FEE are brought out from the
  top PCB through 32 pin FPC connectors. A
  backplane multilayer PCB sits on the chamber PCB
  and carries power planes, control signal tracks
  and FEE board mounting connectors.
• Each FEE board has 64 channel readout and plugs
  onto the backplane. Each backplane accommodates
  72 FEE boards.
• Anode wire of each cell gets the ground reference
  only when the FEE boards are mounted.
• The top and bottom chamber PCBs are metalized on
  the inner face leaving only a thin annular region
  around the anode wire islands. This metalized
  area and the copper honeycomb make an electrical
  contact after assembly and carries the applied
  cathode potential. Thus, only the thin (0.75mm)
  annular gap around the wire-ends isolates the
  chamber voltage and can cause sparks or excessive
  leakage current if the insulation is defective
  due to contamination or rough edges.

3
Readout of Signals
Cathode ( Neg HV)
Anode wire
CSA input stage
Hexagonal cell
Each FEE reads 64 cells through 2 signal
cables Of kapton. Each reads 32.
4
Detector Module

• Each module has 4608 cells.
• Organized in 6 chains.
• Chain reads 768 cells.
• Each chain has 12 FEE boards.
• Each FEE connected to detector by 2 kapton
  cables(232)
• Each chain via Translator board connected to
  DAQ.
• Boards mounted on a backplane
• Sitting on chamber.
• Each chain given Low voltage through
  distribution box.
• Distribution box connected to LVPS (EASY
  modules)

Before mounting FEE
With ,Backplane,FEE, HV, Gas, LV connections.
5
HV Tests of Modules-1

• High Voltage testing procedure for ALICE PMD
  Modules at CERN
• 1) Gas flushing and leak checking(after 2hrs) and
  rectificationmin flushing for 24hrs2) High
  voltage boundary leakage at 1600v to 1700V for
  min 12hrs leakagecurrent normally below 100nA at
  tripping current set to 1 uA and time 0.5sec.
  confirmation of boundary spark is very important.
  before going tonext step.3) Putting shorting
  connectors and debugging near 1500 to 1600Volt
  andsparks and leakage current.4) faulty cells
  and zones are isolated and keep high voltage for
  longertime.this time vary module to module
  depending on faulty nature5) before taking
  module out keep module voltage 1400 to 1500, trip
  time 0.5sec min and maximum current(spark)
  5uA.6) During HV stability test of min 3 hours
  as in stated parameters othermodules are kept at
  lower High voltage to avoid EMI effect.

6
Step-1 DIP switch with long Hv connectors
HV box
Spark monitor
Opto-coupler Based scaler
Fast lt10us 10usltMediumlt80us Long gt80us
Step-3 DIP switch With Kapton cable
Step-2 DIP switch With zone shorting Strip PCB
Leakage Current monitor
1M
DIP switch
Typical module HV seasoning
HV debugging Step-1 chain isolation Step-2 zone
isolation Step-3 single channel isolation
6
Spark rate after few days of HV seasoning
7
Views about HV application
Testing at VECC with shorting connector Testing
was mainly sequential, major time spent on gas
leak repair (iterartion), boundary insulation and
major debugging of cells with HVPS CAEN 470N
(lots of limitation) existing at VECC.
Testing at CERN 581 with shorting
connector Testing was mainly parallel mode (5
stns working), major work is Debugging,
seasoning, durability at 1500 V and 1400 V. HVPS
CAEN SY1527 used where we got flexibility of
setting trip current limit and trip time
smoothly which was never played before.
7
8
Limitation of HVPS with HV filter and Detector

• Major issues
• Frequent tripping should be minimised
• Tripp current limit less than 1uA
• Tripp time limit 0.25 sec to 0.5sec
• FEE board burning by HV should be minimised
• Minimize overloading of HV at High Multiplicity

1M
1M
1M
2.2nF
0.22nF
Same as STAR PMD

• This limits during HV test
• Lowering of trip current below 5uA
• Lowering of trip time below 0.5sec

8
9
These tests were done to check the health of the
modules on arrival at CERN and helped condition
the chambers, diagnose major problems like
boundary sparks, wire shorting etc and pass the
modules for further tests with FEE.
9
10
Testing at point-2 with FEE boards mounted

• Operated with same limit as earlier (1 uA, 0.5s)
  . Found boards going bad, drawing more current.
  Trips less frequent in HV(5micro and1sec) but
  more frequent in LV side.
• Operated with lower limits on HV (1/0.5 micro A
  , 1 /0.5 sec for trip time).
• FEE boards going bad after sparking. HV trips
  followed by LV tripping for one or more chains or
  module. HV and LV trips simultaneously.
• HV limits further reduced 0.2 micro and 0.2Sec
• 3) Still boards go bad and frequency of HV
  trips increases.
• Problems not identified earlier because,
• 1) Modules were not tested with entire
  electronics.
• Spark tests done earlier not enough.

11
Previous tests with Sparks

• When we injected sparks on input channels of
  the chips , boards have not gone bad for MANAS
• Detector capacitance was not taken into account .
• We injected the sparks in one channel only. Here
  capacitance is small.
• With entire electronics mounted , detector
  capacitance is much-more. So boards are going bad
  due to fast-discharge of detector capacitance.
• Possible reason
• Detector capacitance was not considered in the
  these tests
• We sincerely acknowledge the guidance given by
  Jean Claude Santiard of CERN in understanding our
  problems and helping us in carrying out the tests
  to solve this problem.

12
Issues with operations

• Sparks are damaging the channels of the FEE board
  in spite of built in ESD protection with MANAS .
• Lowering the limit of HV (0.2µA and 0.2 Sec) is
  not helping to save the channels. Frequency of
  trip increases with lower limits.
• When channel goes bad, LV current increases. So
  chain current crosses set limit of LVDB(Low
  Voltage Distribution Box) and trips. The chain
  remains off .( if faulty condition persists)
• With frequent sparks many channels may go bad.
  Corresponding chains will be tripped off.
• So this way running the detector is too difficult
  where access is limited.

13
Capacitance Measurement
Detector capacitance - Capacitance between
cathode and all anode wires shorted.
For each row (6 boards) 320pf (6zones) Total
value for 12 rows 4nf (approx) No Of cells
4608
Scale 20nF ( on meter)
detector module
Cathode
anode wires shorted
14
Test Set up
HV In
HV Out
R
R
R
From HV unit
C det
GND
Cdet is added to include effect of detector
capacitance
R
(Series resistance)
Section of inner face Chamber PCB

Test board is used to test the full functionality
test of FEE board. It can be mounted with
Translator board and one FEE board. Signal can be
injected via CAL pulse as well as signal cable
with the help of input Pulser.
FEE Board
Test-board Setup
15
How we tested

• Tests on single FEE board with and without
  simulated capacitor
• Injected the spark into one of input channels of
  MANAS.
• 2) No channel went bad when we have not added
  any capacitor (Cdet) .
• 3) Adding 220 PF (Cdet) from cathode to GND do
  not cause any damage
• 4) Increasing value to 500 PF (Cdet) channel
  goes bad without resistance. LV current
  increases.
• With 500 PF and adding 100ohms resistance we
  have seen that channel do not go bad even after
  lots of sparks.
• With detector and single FEE board(equivalent
  capacitance for one board 200pf approx), we
  tested till 2KV and 10micro Amp 1sec. No damage
  was seen.
• Tests with FEE boards chain and detector
• Tested one chain with FEE with no
  resistance(Equivalent detector capacitance for
  one chain of 12boards 470pf approx). One
  channel after every spark goes bad
• Repeated the same with resistance 100 ohms (0603
  Size) for a chain. Spark jump over seen.
• Repeated with 470 ohms(1206 size) for one chain.
  Did not see spark jump over. Channels are not
  going bad. OK.
• Test for one complete module with these resistors
  underway.

16
Test results with FEE boards

• FEE Board Det capacitance 
  Series Resistance Result 
  
  
• --------------------------------------------------
  --------------------------------------------------
  ---------------------------
• FEE (on test board) -
  -
  No Damage
• MANAS (external diodes) 5nf(simulated)     
  No             Goes bad.
• MANAS(external diodes) 5nf(simulated)     
  Yes                
  OKMANAS         5nf(simulated)    
  No          Goes badMANAS      
     5nf(simulated) 
  Yes            OK
• FEE(on Test board) 200pf(simulated)
  - No
  Damage
• FEE(on Test board) 500pf(simulated)
  -
  Damage
• FEE(on Test board) 500pf(simulated)
  100 Ohms /0603 size No Damage
• 12FEE(on Backplane) 470pf
  -
  1ch for each spark.
• 12FEE(on Backplane) 470pf
  100 Ohms,0603 size spark jump over
  seen
• 72FEE(on Backplane) 1.1nf
  470 Ohms/1206 size Ok(tests going
  on)
• --------------------------------------------------
  --------------------------------------------------
  --------------------------
• From above observations and results this can be
  concluded that ESD has major effect in burning
  channels which is due to fast discharge of the
  detector capacitance into FEE channels.
• Note MANAS signifies that test is done on star
  like board with MANAS chips

17
Comparison of results with and without resistance
Gain spread
With R2 470ohms
Without R2
With R2 560ohms
We tested 2 boards with and without resistance.
With 470 ohms there is minimal changes in gain
spread. With 560 Ohms we have seen few channels
showing more gain and overall gain spread is
increased .
18
Theoretical Calculations

• General current equation for discharge by a RC
  network
• I (V/R)exp(-t/RC)
• Effect due detector capacitance includes
  following parameters
• With V1500V, R 200 ohms and C 1nf (measured
  with all FEE) ,
• And including the R,C values of HV filter box

I (1500/200) exp(-t / 200X10-9) (1500/106)
exp(-t / 220X10-6) (1500/2X106) exp(-t /440X10-5
19
Results with and without R2
In this case cur can rise up to 10A for a
short time
Without R2
With R2470ohms
In this case current is not rising more than 2A
even for short time.
20
With these results and observations We propose
to add R2 now
MANAS has D1,D2,R1 internally built-in
A temporary arrangement of resistors on existing
kapton cables
21
Detector module under test
DAQ-PC
Agilent Pulser
LVDB
Patch panel
Detector with FEE
HV Box
CAEN 470-HV
22
Summary of the investigations so far

• Damage of boards with sparks is due to detector
  capacitance.
• Improved behavior is seen after adding of series
  resistance. This is must and should be between
  anode wire and input of MANAS.
• No LV trips , after sparks seen like earlier.
  Boards have not gone bad.
• No increase in current drawn by boards seen after
  HV trips .
• Complete testing of one module is going on to
  confirm the investigations.
• Further testing should make sure that there is
  no unforeseen problem left behind.

23
Spark nature and energy dumping
Secondary breakdown parameter during spark
stored energy (joules) dumped from Capacitors as
stated earlier. In case of capacitor this is ½
CV2 or instant discharge is I.V.t or product of
instant current, voltage and spark duration
time. Typically energy dump during a spark may be
50 to 100 micro joules and high magnitude of
this is responsible for FEE board burning.
Spark seen through HV box using opto-coupler in
series
Spark seen through shorting connector using
opto-coupler, case may be similar with FEE
Peak current may 100 to 250 uA
23
Lab made Opto-coupler calibration 150uA/volt
24
Could there be alternate solutions ?

• Adding resistance seems to help. This has been
  investigated a lot and is under very active
  consideration. Implementation can be well
  organised and achieved within a given time frame
• Could one also think of a crow-bar type device ?
  This is under consideration but not much
  progress.
• Expert suggestion will help us speed up the
  proper implementation.

25
Possible time frame for implementing resistors

• Components for one module ordered, tests to be
  completed by 15.2
• If tests are positive and experts agree, we shall
  make mass order for kapton and resistors, expect
  them by mid-March, assembly of resistors on
  kapton etc. can be organised on war footing at
  Kolkata
• Can begin series testing of modules at CERN by
  early April.