VLSI Critical Design Review Complex Number Multiplier

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VLSI Critical Design ReviewComplex Number
Multiplier

• John Ogembo
• Zach Smith

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Outline

• Goals and Specifications
• Design Process
• Simulation and Timing Diagrams
• Achieved Design Specification
• Next Step

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Goals and Design Specifications

• Working chip
• Target speed 100 MHz
• Fixed point integer
• 2s complement format wherever signed numbers are
  used
• 16 bit vector Complex Numbers

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Goals Design Specifications (Cont)

• synchronous logic operates on a rising edge of
  the clock
• inputs are sampled on a rising edge of the clock
• outputs are updated on a rising edge of the clock

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Design Process

• 4 Multipliers
• 2 Adders
• 5 pipelining registers

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Small

• 2 x 8 bit input
• 8 bit output

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Initial Multiplier Design

• Advantages
• Size, power
• Disadvantages
• Slow
• Multiple clock cycles to perform operation
• Complicated to debug

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New Multiplier Design

• 8 bit input Multiplier
• Single cycle
• Uses Cells

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Multiplier Inputs

• Zoomed Inputs

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Multiplier Outputs

• Zoomed Outputs

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Large

• 2 x 16 bit inputs
• 16 bit output

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Inputs

• Zoomed Inputs

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Outputs

• Zoomed Outputs

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16 bit Adder With Overflow

• This adder performs
• S gt 01111111, (max)
• S 01111111 (127)
• S lt 10000000 (min)
• S 10000000 (-128)

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Addition Problem

• Notice
• 0000
• 1110
• 1110

0111 0111 1110
0 (-2) -2
7 7 14
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Addition Problem

• Problem It is impossible to tell the sign of any
  output from the adder. This is needed to
  determine the sign of the default overflow output
• Solution Use logic based on the inputs and
  outputs to determine the sign of the output

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Addition Problem
Overflow detection
Multiplexer
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16 bit Substractor Inputs

• All the bits in B must be complemented and an
  extra one added using Cin

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Multiplier Timing Diagram

• This is the worst-case scenario timing of the
  multiplier,
• 01111111
• x 01111111
• This takes 9 ns

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Substractor Timing Diagram

• Worst scenario
• Operation of (-1)-(-1) 0
• This takes 7.8 ns

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Achieved Design Specification

• Clock speed of about 109.9 MHz
• Correctly multiplies signed, fixed-point, complex
  integers.

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Next Step

• Layout
• Power consumption
• Area
• Decide which design should we use for our chip