Mo Missous

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DS4-T1FRONT-END TECHNOLOGIES
FRONT-END TECHNOLOGIES Mo Missous Microelectroni
cs and Nanostructures School of Electrical and
Electronic Engineering University of Manchester
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DS4-T1FRONT-END TECHNOLOGIES

• PARTICIPANTS

Manchester InP technologies for LNA and High
Speed ADC. ASTRON GaAs LNA ( with
OMMIC) OPAR SiGe LNA ( with Philips)
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DS4-T1FRONT-END TECHNOLOGIES

• AIMS
• To develop active semi-conductor devices and rf
  amplifier systems, including high speed Analogue
  to Digital Converters (ADC), optimised
  specifically for radio astronomy applications
  (rather than commercial and military one).
• GOALS
• To combine low noise, high linearity and low
  power dissipation with low cost manufacturability
  . Achieving these aims involves a combination of
  materials (GaAs, SiGe and InP) and topologies
  (lithography).
• This will require development of customised
  active device technology, and the use of novel
  design techniques.

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DS4-T1FRONT-END TECHNOLOGIES
Basic Semiconductor Technologies (MANCHESTER
) Design and Fabrication, using a first
generation 1µm optical lithography process, of
Low Noise InGaAs-InAlAs pHEMT with improved
breakdown voltages and with adequate noise figure
(lt 35K at 1.4 GHz ). Design and Fabrication of
high Speed InGaAs-InP HBT with FT gt 70 GHz but
still based on the same optical lithography
process .
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• 1.(a) High Breakdown Voltage/Low noise pHEMT

Figure 1 Comparison of Gate-Source diode I-V
for conventional (VMBE1855) and newly developed
structure (VMBE1831).
Figure 2. Comparison of optimum noise figures of
the improved (VMBE1831) and conventional
(VMBE1855) pHEMTs
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• 1.(b) Wide Band LNA Designs based on developed
  pHEMTs

Figure 3 Wide Band (0.4 -2GHz Feed back
Amplifier based on 1 µm InGaAs-InAlAs pHEMT
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• 1.(b) Wide Band LNA Designs based on developed
  pHEMTs

-Stability (stable 0-30 GHz) -Noise (NF1.2
0.3 dB) 0.4-2 GHz -Gain ( Gain21 2 dB) 0.4-2
GHz
Figure 4 Wide Band (0.4 -2GHz Feed back
Amplifier based on 1 µm InGaAs-InAlAs pHEMT, rf
characteristics.
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• 2.(a) High Speed InGaAs-InP HBT

implementation.

Figure 5 5?5?m self-aligned HBT (a)
Common-emitter output characteristics (b)
Collector current versus fT. Simulated and
Measured characteristics
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• 2.(b) 4 bit 4Gs/s ADC Designs

Anti- Aliasing (1)
Figure 6 High Speed Flash ADC building Blocks
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• 2.(b) 4 bit 4Gs/s ADC Designs

Figure 7 Captured results from simulation of the
comparator array at 4GHz clock and (a) 0.25GHz
and (b) 1GHz input signal frequency
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DS4-T1FRONT-END TECHNOLOGIES

• 2.(b) 4 bit 4Gs/s ADC Designs

The basic building blocks to produce low power
ADCs are currently being investigated. The
initial results for the transistors suggest these
can operate effectively at extremely low bias
voltages. The simulations for the comparator of
the ADC show promising progress, providing a
relatively low power consumption of 1.73W at
larger geometries. With further optimisation of
the epilayer design, transistor geometry ( 1x3
emitter sizes) and circuit layout, an ultra-low
power, GHz class ADC looks increasingly possible
using this technology.
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ASTRON concentrated on the use of existing
Integrated Circuit processes with a strong focus
on III/V technologies for the implementation of
Low Noise Amplifiers.
3 (a). Dual Feedback LNA
Dual-loop negative feedback amplifiers are
suitable for both wideband and low noise
applications. Compared to the conventional
inductive-degenerated low noise amplifiers, the
dual-loop feedback amplifier offers well-defined
input impedance and signal transfer function and
potentially good noise performance
simultaneously. The dual-loop power-to-power
configuration is mostly used for applications
that have a well-defined source and load
impedance, since its input impedance depends on
the load and the output impedance depends on the
source. The dual-loop power-to-voltage and
power-to-current configurations do not have these
limitations and are therefore very suitable for
active antenna applications.
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Figure 8 Schematic and Simulated performance of
the dual feedback LNA
This has been implemented in 0.2µm GaAs
technology from OMMIC, partner in SKADS. A very
good input impedance match combined with a good
noise match has been achieved. Measurements of
the realized device are in progress.
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3 (b). Differential Low Noise Amplifier Design
In order to avoid the need for a balun
(balanced-unbalanced) circuit between the antenna
and the LNA, a differential LNA concept has been
implemented in InP (NGC) and GaAs (OMMIC). The
differential LNA can be connected directly to the
differential antenna concepts like the Vivaldi
antenna. For the intermitted impedance levels
non-50 Ohm impedance can be selected in order to
avoid further matching circuitry losses.
Characterization of these circuits is however
very complicated. This will be described in more
detail in the DS4-T4 presentation, wide band
integrated antennas.
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3 (c). CMOS Low Noise Amplifiers
A standard LNA concept has been implemented in
0.18µm CMOS technology from UMC. The impedance
and noise matching on the input requires an
off-chip transmission line, limiting the
frequency band width somewhat. The measured noise
figure reaches the 0.5dB as can be seen from the
plot below.
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Figure 9 Simulated and measured results of the
CMOS LNA
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OPAR contribution in DS4-T1 is centered on the
use of low cost Si based technologies for the
design of basic building blocks of SKA such as
filters and wide band LNAs.
4. (a) Filter design in PICS technology PICS is
a low cost 1µm Silicon technology available from
Philips Semiconductors that offers high quality
passives and the ability to achieve a highly
integrated System in Package by using the
substrate itself for interconnecting different
dies that may be made from different materials
for building a super-die. This low cost
technology coupled with its capability to achieve
high integration can be very valuable in tackling
cost issues for SKA.
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Filter design Two band pass filters have been
designed, a 5th order Tchebytchev band-pass
filter and a high pass filter cascaded with 1 (or
2) low pass filter.
Figure 10 Microphotograph and transmission of
the Tchebytchev band-pass filter
Both filters show good agreement with the
simulations. Results from this first iteration
are good enough to allow a second step follow up
that will use this substrate and a next iteration
of this filter as an interconnect substrate to
realize a LNA/filter combination on a super-die.
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4. (b) SiGe LNA
The QuBiC4G SiGe technology from Philips
Semiconductors was used ( 0.25 µm). This
technology exhibits a minimum noise figure NFmin
of 0.6 dB at a frequency of 2 GHz. Another
technology, QuBiC4X that is a SiGeC technology
even achieves a NFmin of 0.4 dB. Its use will be
assessed in the next stage.
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In order to assess the potential of Silicon based
technologies for wide band LNA, a 300 MHz 2 GHz
amplifier both in single ended and in
differential configuration have been designed.
Figure 11 Layout and noise figure of the
differential 300 MHz 2 GHz QuBiC4G LNA
The minimum noise figure (0.9 dB _at_ 2 GHz) is
close to the minimum noise figure of the
technology (0.6 dB_at_ 2 GHz). The noise figure is
as low as 0.93 dB around 700 MHz and is below 1.2
dB from 300 MHz to 2 GHz.
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Figure 12 Gain and matching of the differential
300 MHz 2 GHz QuBiC4G LNA
We have demonstrated that it is possible to
design a wide band LNA in the 1 dB NF range with
a flat gain and good input and output matching
using a low-cost commercially available 0.25 µm
Silicon technology. We hope to decrease still
further this value as technologies with lower
NFmin become available.
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Achieved milestones and deliverables
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NEXT 18 MONTHS STAGE July 2006 to Jan 2008 LNA
design techniques simulation study determine
optimum design approach, including consideration
of circuit topologies best suited for achieving
wide operating bandwidth, linearity, low noise
temperature, high yield and low cost (T015 to
T036). ADC building blocks design, fabrication
and performance (T012 to T030) Design,
manufacture and test of hybrid LNA using novel
discrete devices developed in programme (two
iterations) (T018 to T024). Fabricate and test
Integrated ADC circuits (T018 to T030)
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TABLE 1 Schedule for DS4-T1 The Gantt chart for
these tasks remains on target.
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ACKNOWLEDGEMENTS

• Jan Geralt Bij de Vaate
• Jaques Pezzani
• Joz Sly
• James Sexton
• A. Bouloukou
• Sobih
• Plus many, many more!