USB 2.0 Compliance Program Overview

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USB 2.0 Compliance Program Overview

• Dan Froelich
• Intel

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Agenda

• USB-IF Compliance Testing History
• Goals of the USB 2.0 Compliance Program
• USB 2.0 Differences from USB 1.1
• New/Modified Compliance Tests
• Electricals
• USBCheck
• Transaction Translator
• System/Platform
• High Speed Signal Quality Test Demonstration

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History

• USB-IF 1.1 Compliance Program
• Long evolution from 1996 (USB 1.0) to today (2000)

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Compliance Program Evolution

• The USB 2.0 Compliance Program is an extension of
  the USB 1.1 Compliance Program
• Years of experience
• Tools already in place

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Goals of theCompliance Program

• High Quality USB 2.0 Products
• Stable, Repeatable, Well Documented Tests
• Documented Test Procedures
• Documented Test Assertions and Descriptions
• Instantly Available Testing (Qualified Test
  Houses)
• Leverage USB 1.1 Compliance Program
• Reuse USB Check
• Reuse Interoperability Test Procedures
• Reuse Full and Low Speed Electrical Testing
• Minimize Test Equipment Costs

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Compliance Program Milestones

• HS Testing Preview at October PlugFest
• HS Signal Quality and TDR
• USBCheck
• TT Functional Testing
• Logo Testing Availability
• Schedule Testing at Intel Peripheral Integration
  Lab
• Starting in November
• Contact Dan Froelich, daniel.s.froelich_at_intel.com
• Available at Plugfests in January
• All Test HW and SW Available by Q3 2000

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USB 1.1 Testing Modifications and Reuse

• Power Measurements
• USBCheck
• Chapter 9 Additions
• Chapter 11 Additions
• Interoperability
• HS Device and Hub Additions
• USB 1.1 Test Fixtures
• Droop/Drop
• Inrush
• FS/LS Signal Quality

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USBCheck Chapter 9 Additions

• Other Speed Device Qualifier andConfiguration
  Descriptors
• HS/FS Devices Must Use In Either Environment
• Standard Configuration Descriptors OnlyFor
  Current Environment
• Endpoint Packet Size and Interval Rules
• Electrical Test Mode Support
• HS Devices Tested At High and Full Speeds

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Compliance Tool USBCheck
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USBCheck Chapter 11 Additions

• TT RequestCodes
• Port Indicators
• New Status Bits

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Interoperability Testing

• Same Tree For HS/FS/LS Testing
• Similar To 1.1 Interopability
• All Transfer Types
• 5 hubs deep with 5 meter cables (i.e. Tier 6)
• Mix of speeds
• Test devices at both Fulland High Speeds

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Existing Test Fixtures

• Current
• Inrush
• Drop

• Droop
• Full/Low Speed Signal Quality

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What Changed For USB 2.0

• HS Electrical Signaling and Electrical Test Modes
• Defined Receiver Characteristics
• Repeatable Signal Quality Testing
• Hub Transaction Translator for FS/LS Support
• Other Speed Device Descriptors
• Model Largely Unchanged
• Device Framework
• Power Management and Distribution
• Cables, Connectors, and Topology

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New Testing Areas

• Electricals
• High Speed Signal Quality
• Time Domain Reflectometry (TDR)
• Receiver Sensitivity and Squelch
• Platform Testing
• Electricals
• Port Routing
• More Extensive Hub Testing
• High Speed Repeater
• Transaction Translator

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USB 2.0 ElectricalTest Modes

• High-speed Capable Devices/Hubs Must Support Test
  Modes
• Test modes Enable Repeatable Testing
• SetFeature(TEST_MODE) and SetPortFeature(PORT_TEST
  ) Requests Provide Standard Means of Entering
  Mode
• Exit Action is also Standardized
• Upstream Facing Port Power Cycle
• Downstream Facing Port Hub Reset

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Test Points

• Transmitter
• Receiver (New)

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New Test Fixtures
Diff Probe
Data Generator

• Device and Host Tests
• Signal Quality
• TDR
• Receiver Sensitivity
• Chirp
• J and K Levels

90 Ohms
Initialization Port
Test Port
HS Relay
Vbus1
Vbus2
Power Selection Ckt
Vcc
Gnd
Usb 2.0 Test Fixture
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High Speed Signal Quality

• USB 2.0 Spec Defines Required Eye Patterns
• 6 Patterns
• 4 correspond to external connectors (TP2 TP3)
• 2 correspond to internal connectors (TP1 TP4)
• Rise / Fall Times
• Allowance for Jitter
• Overshoot / Undershoot
• Testing at External Connectors
• New Test Fixture for HS Signal Quality Available
  Soon

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HS Signal QualityTest Procedure

• Put Device in Test Mode Test_Packet
• Flip Test Fixture Relays To Route Output to 90
  Ohm Termination
• Capture Waveform
• Analyze Data

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HS Receiver Sensitivity and Squelch Test Procedure
Data Generator
Test Mode SW

• DUT Placed In Test_SEO_NAK Mode
• Data Generator Generates IN Packets
• Device Must Respond For In Spec Packets
• Device Must Not Respond to Out of Spec Data
  Generator Output

USB 2.0 Test Fixture
SMA
HS Relay
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Time DomainReflectometer (TDR)

• Means of Measuring a Receivers Impedance
• Receiver idle D, D- both at 0 volts (Test Mode
  SE0_NAK)
• Requires NewTest Fixture
• To be run onAll Devices,Hubs, and Platforms

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TDR Test Procedure
TDR

• Device Under Test Placed In Test_SEO_NAK Mode
• Relay Switches Idle Data Lines to TDR
• TDR Broadcasts Test Signal
• TDR MeasuresSignal Reflections ToDetermine
  Termination And PCB Impedance

Test Mode SW
USB 2.0 Test Fixture
SMA
HS Relay
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CHIRP Test Procedure

• CHIRP Testing
• Measured with single ended probes
• At the A-connector (TP2)
• Important Parameters
• Reset duration
• CHIRP K amplitude
• CHIRP K duration
• HS termination timing
• Host CHIRP amplitude

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Platform Testing

• Eye Pattern Testing at TP2
• Template 1 (Transmit)
• Template 4 (Receive)
• TDR Testing
• Port Routing

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Port Routing Logic
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Extensive Hub Testing

• Signal Quality Eye Patterns
• At TP3 (downstream) in addition to TP2 (upstream)
  
• Both Transmitting (Template 1) and
  Receiving(Template 4)
• Hub Specific Commands
• Port Test Modes
• TDR Testing
• All connectors (upstream B, downstream A)
• Transaction Translator
• Electrical HS Repeater Testing

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Transaction Translator

• What is a Transaction Translator?
• Component of the hub that handles data transfers
  to/from full and low speed downstream devices
• When is it Used?
• Active when hub is configured at high speed and
  full and/or low speed devices connected
  downstream
• Buffers data transfers
• Finite space
• 2 kind of Buffers - Periodic and Non-Periodic
• 1 TT per hub OR 1 TT per port

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Transaction Translator
Hub Components
High speed connection
Hub Repeater
Hub State Machines
TTN
TT2
Hub Controller
Routing Logic
TT1
Port 2
Port 1
Port N
480 MHz
12 MHz
1.5 MHz
HS Device
LS Device
FS Device
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Transaction Translator Testing

• Devices Hubs of Mixed Speeds Below Hub
• Rigorous Functional Tests With FS/LS Devices
• Proper Enumeration of Devices
• Perform LoopBacks (All Transfer Types)
• Stress Periodic and Non-Periodic Buffers
  (Multiple Endpoints)
• Check for Isochrony Hiccups
• Data Integrity
• Specific Test Cases For Possible Device Behaviors
• Timeout, Stall, Protocol Violations, ETC

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Oscilloscope Requirements

• List of Required Scope / Probe Capabilities
• 5 G Samples/sec (Per Channel)
• 2 GHz bandwidth
• Accuracy Requirements
• Tested Scopes and Probes
• Scope TDS 694C 10 GS/s, 3 GHz
• Probe P6217 Fet probe 4 GHz, 0.4 pf typ
• More Scopes and Probes to be added

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Conclusions

• Two significant Additions for USB2.0 Compliance
• Electrical Testing
• HS Signal Quality
• TDR
• Receiver Sensitivity
• Squelch
• Transaction Translator Testing
• Well Documented Tests
• Test Procedures
• Test Specifications

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Demo

• High Speed Signal Quality
• Using Test Mode Test_Packet

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Questions?