Project Presentations DUALLOGIC - PowerPoint PPT Presentation

Title: Project Presentations DUALLOGIC


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Project Presentations - DUALLOGIC
Speaker

• Dr  Androula Nassiopoulou
•    Director of IMEL/NCSR Demokritos
•    Athens, Greece
• A.Nassiopoulou_at_imel.demokritos.gr

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Agenda / content

• DUALLOGIC project - Main concept - Objectives
• Project components - Main processing Modules
• Dual channel front-end CMOS
• Consortium
• Exploitation
• Contact details

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DUALLOGIC Dual Channel CMOS for sub-22 nm High
Performance Logic The flagship of CMOS in
FP7-ICT Budget 9.1 M EURO EC Funding 5.8 M
EURO Start date 01-12-2007 / Duration 36
months
Project leader A. Dimoulas NCSR
DEMOKRITOS Athens, GREECE
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Main Concept
Front-end CMOS with high-mobility channels as an
option for sub-22 nm nodes to break the
performance barrier
Why dual channel ? Ge works well only for
pMOS III-V works better for nMOS
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Objectives

• Short channel (70 nm) Ge pMOS and III-V nMOS
• -Verify mobility advantage at short gate lengths
  
• -Demonstrate superiority over Si devices
• Co-integration of Ge pMOS and III-V nMOS on the
  same
• engineered substrate based on GOI
• -Use a 200 mm/65 nm pilot line to demonstrate
• scalability and manufacturability
• Take-up of project results to a wider sub-22 nm
  technology platform on 300 mm

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Project Components
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Main Processing Modules The DUALLOGIC backbone

• Development of 200 mm localized GeOI by Ge
  condensation as a starting substrate
• -Starting substrates
• Development and manufacturing of MOCVD tool
• for selective epitaxy of III-Vs on Ge
• -Dual Channel Engineered Substrates
• Co-integration in a 65 nm/200 mm pilot line
• -Dual channel high-m front-end

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Local GeOI starting substrates
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Dual channel engineered substrates
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Dual channel front-end CMOS
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Consortium (1)
DEMOKRITOS Co-ordinator IMEC
IBM -Zurich
CEA-LETI ST Micro

Gate dielectric development Co-integration in
200 mm pilot line Epi-device III-V layers
200 mm Localized
GOI Testing and Benchmarking
Research Center Technology Development
Lab IT Systems Technology
Development Lab Integrated Device

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Consortium (2)
NXP AIXTRON
U. Glasgow KULeuven
Semiconductor industry Semiconductor Equipment
Manufacturer University University
Circuit Design III-V Selective Epitaxy MOCVD
Tool Device modeling III-V contacts Structura
l Physical Characterization
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Exploitation
STEP 1 in 3 years Further development in a wider
sub-22 nm technology platform on 300 mm
-Incorporate back-end and combine with device
architecture changes Demonstrate generic
IC -Funding from EU Framework Programs
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Exploitation
STEP 2 in 6 years from now Full CMOS integration
in an industrial platform -Integrate HP Logic
with DRAM, NVM additional functionality -Fundi
ng EUREKA-MEDEA and/or ENIAC JTI
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More Information
DUALLOGIC Web EETimes Interview Semiconductor
International Press Release
http//www.ims.demokritos.gr/DUALLOGIC
http//www.eetimes.eu/industrial/206800002
http//www.semiconductor-today.com/news_items/2008
/FEB/DUALLOGIC_110208.htm
http//www.semiconductor.net/article/CA6531036.htm
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Thank you
Contact details Dr. A. Dimoulas, project
leader Institute of Materials Science NCSR
Demokritos Athens, Greece E-mail
dimoulas_at_ims.demokritos.gr