The CORDIC Algorithm

1
The CORDIC Algorithm

• By
• Mohammad Kharashgeh
• Hardik Jambusaria
• Wei-Li Chen
• Donald Guelich

2
CORDIC

• Acronym for Coordinate Rotations Digital
  Computer.
• First designed in 1950s
• Computes trigonometric and some other special
  functions.

3
CORDIC idea
4
CORDIC trick

• x(i1) x(i) cos a - y(i) sin a
• y(i1) y(i) cos a x(i) sin a
• x(i1) x(i) - y(i) tan a
• y(i1) y(i) x(i) tan a
• Choose angles that has tan powers of 2

5
Forming angles

• We use these angles to form all other angles 45,
  26.6, 14, 7.1, 3.6, 1.8, .9, 0.4
• 30 45 -26.614 -7.13.61.8 -0.90.4
• 90 4526.6147.1-3.61.8 -0.90.4

6
Project Objectives

• Going through the whole process of project
  design from specification to silicon!
• More experience in using tools
• More experience in using VHDL
• Group work

7
Schedule

• 10th March CORDIC specification
• 23rd March Component designs
• 28th March State machine design
• 3rd April System simulation and testing
• --------------------------------------------------
  ---
• 20th April Synthesizing CORDIC
• 25th April Post vs. Pre Synthesis simulation.
• 1st May Power and timing optimizations
• 8th May Layout and refinement

8
Top level diagram
9
Fixed point representation
10
Block Diagram
11
Main Components

• Two shifters
• A lookup table
• Two 9bit adders
• A 16bit adder

12
VHDL Components

• COMPONENT shifter IS
• PORT( abc IN STD_LOGIC_VECTOR( 2 DOWNTO 0)
  data_shi IN STD_LOGIC_VECTOR( 8
  DOWNTO 0 ) data_out OUTSTD_LOGIC_VE
  CTOR( 8 DOWNTO 0 ))END COMPONENT
• COMPONENT lookuptable IS
• PORT( address IN STD_LOGIC_VECTOR( 2 DOWNTO 0
  ) data OUT STD_LOGIC_VECTOR( 15
  DOWNTO 0 ))END COMPONENT
• COMPONENT adder9bit IS
• PORT( operand1 IN STD_LOGIC_VECTOR( 8 DOWNTO 0
  ) operand2 IN STD_LOGIC_VECTOR( 8
  DOWNTO 0 ) operation IN
  STD_LOGIC result OUT
  STD_LOGIC_VECTOR( 8 DOWNTO 0 ))END COMPONENT
• COMPONENT adder16bit IS
• PORT( operand1 IN STD_LOGIC_VECTOR( 15
  DOWNTO 0 ) operand2 IN
  STD_LOGIC_VECTOR( 15 DOWNTO 0 )
  operation IN STD_LOGIC
  result OUT STD_LOGIC_VECTOR( 15 DOWNTO 0
  ))END COMPONENT

13
Lookup table for CORDIC
14
Lookup table code

• Architecture design OF lookup IS
• BEGIN
• PROCESS(address)
• BEGIN CASE address IS
  WHEN "000" gt data lt "0010110100000000"
  WHEN "001" gt data lt "0001101010011000"
  WHEN "010" gt data lt
  "0000111000000000" WHEN "011" gt
  data lt "0000011100011000" WHEN
  "100" gt data lt "0000001110011000"
  WHEN "101" gt data lt "0000000111001000"
  WHEN "110" gt data lt "0000000011101000"
  WHEN "111" gt data lt
  "0000000001101000" WHEN OTHERS gt
  data lt "0000000000000000"
  END CASE END PROCESSEND design

15
Lookup simulation
16
Shifter specification

• Always shifts right
• Variable length
• Parallel (shifting by 1 or 7 takes same time)
• Sign extension

17
Shifter dataflow schematic
18
Shifter simulation
19
Shifter synthesis
20
Adders specification

• Two size of adders used (9 and 16 bits)
• An input signal determines addition or subtraction

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Adder/ subtractor 9bit

• USE IEEE.STD_LOGIC_ARITH.ALL
• USE IEEE.STD_LOGIC_UNSIGNED.ALL
• ENTITY adder9 IS
• PORT( operand1, operand2 IN STD_LOGIC_VECTOR( 8
  DOWNTO 0 )
• operation IN STD_LOGIC
• result OUT STD_LOGIC_VECTOR( 8 DOWNTO 0 ))
• END adder9
• ARCHITECTURE a9 OF adder9 IS
• BEGIN
• PROCESS( operand1, operand2, operation )
• BEGIN
• IF operation '0' THEN
• result lt operand1 operand2
• ELSIF operation '1' THEN
• result lt operand1 - operand2
• ELSE NULL
• END IF

22
Adder9 simulation
23
adder16

• Same design as adder9
• Used for angle (addition / subtraction)

24
System operation

• The asynchronous reset is used to initialize the
  system.
• When the reset is asserted
• Internal signals x and y are set to initial
  values.
• X lt 010011011
• Y lt 000000000
• Internal signal z is set to the input angle.
• Upon rising edge of clock
• For the first 7 clock cycles, the CORDIC
  algorithm executes.
• For the 8th clock cycle, the sin and cos outputs
  are updated.

25
State Machine Code

• PROCESS( clock, reset )
• BEGIN
• IF reset '1' THEN
• x lt "010011011"
• y lt "000000000"
• z lt angle
• count lt "0000"
• ELSIF clock'EVENT AND clock '1' THEN
• IF count "1000" THEN
• cos lt x
• sin lt y
• ELSE
• x lt x_out2
• y lt y_out2
• z lt z_out2
• count lt count 1

26
System Timing

• The shifter requires 8 clock cycles to before the
  CORDIC can update sin and cos.

27
Frequency

• The simulation was run at 20 MHz to check for
  functional correctness.
• In order to increase the speed of the chip, weve
  chosen parallel I/O between the functional
  blocks.

28
Simulation

• Input
• angle 00011110 00000000 30
• Outputs
• sin (angle) 010000000 0.5
• cos (angle) 011011111 0.87109375

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Error analysis

• Two types of error
• Error from representing the angle discretely
• Since we form the angle from adding and
  subtracting 8 other angles, some error will be
  introduced.
• Error in sine and cosine
• Since Our CORDIC algorithm uses 8 iterations to
  compute sine and cosine and for that it uses 8
  bit fraction precision. From our initial
  simulation, the error is shown as

Sim Actual 0.87109375
0.866025404 Actual
0.866025404
Error 100
100
0.005852
30
Future Work

• Increase precision
• Synthesis of the whole chip
• Post synthesis simulation and testing
• Optimize speed and area
• improving power scheme
• Layout and design refinement

31
References

• 1 Ray Andraka. A survey of CORDIC algorithms
  for FPGA based Computers.
• 2 Behrooz Parhami. Computer Arithmetic
  algorithms and Hardware design.