Data Hazards and Stalls

1
Data Hazards and Stalls

• Data hazards and forwarding
• Data Hazards and Stalls

2
An Example
Assuming that register R2 10 initially. And
the sub instruction will result in R2 -20.
3
See PH Fig. 6.28 3rd Ed or 4.52 4th Ed
Pipelined dependencies in a five instruction
sequence using simplified datapaths to show the
dependencies.
Note only add and sw get the right value R2 -
20
4
An Example (contd)
Hazard condition (between sub and and at the
indicated stages) EX/MEM.RegisterRd
ID/EX.RegisterRs 2 General
1a. EX/MEM.RegisterRd ID/EX.RegisterRs 1b. EX/ME
M.RegisterRd ID/EX.RegisterRt 2a. MEM/WB.Registe
rRd ID/EX.RegisterRs 2b. MEM/WB.RegisterRd
ID/EX.RegisterRt
Question can you identify which of the 4
conditions here captures the hazards condition
between sub and or ?
5
Forwarding/Bypassing

• ALU inputs can also from pipeline registers.
• Extra multiplexors.
• Hazard detection units.

6
See PH Fig. 6.29 3rd Ed or 4.53 4th Ed

• The dependencies between the pipeline registers
  move forward in time, so it is possible to supply
  the inputs to the ALU needed by the and
  instruction and or instruction by forwarding the
  results found in the pipeline registers rather
  than stall.

7
See PH Fig. 6.30 3rd Ed or 4.54 4th Ed
The ALU and pipeline register before adding
forwarding.
8
See PH Fig. 6.30 3rd Ed or 4.54 4th Ed
Forwarding control and the multiplexors are added
9
See PH Fig. 6.31 3rd Ed or 4.55 4th Ed
The control values for the forwarding
multiplexors.
10
Forwarding Conditions

• 1. EX hazard
• if(EX/MEM.RegWrite
• and (EX/MEM.RegisterRd ? 0)
• and (EX/MEM.RegisterRd ID/EX.RegisterRs))
  ForwardA 10
• if (EX/MEM.RegWrite
• and (EX/MEM.RegisterRd ? 0)
• and (EX/MEM.RegisterRd ID/EX.RegisterRt))
  ForwardB 10

11
Cond

• 2. MEM hazard
• if(MEM/WB.RegWrite
• and (MEM/WB.RegisterRd ? 0)
• and (MEM/WB.RegisterRd ID/EX.RegisterRs))
  ForwardA 01
• if(MEM/WB.RegWrite
• and (MEM/WB.RegisterRd ? 0)
• and (MEM/WB.RegisterRd ID/EX.RegisterRt))
  ForwardB 01

12
Note Here both EX and MEM stages may have the
exact hazard conditions. What should we do ?
Priority in Forwarding

• Add 1, 1, 2
• Add 1, 1, 3
• Add 1, 1, 4
• .

13
Note When both EX and MEM stages may have the
exact hazard conditions.
Priority in Forwarding

• if (MEM/WB.RegWrite
• and (MEM/WB.RegisterRd ? 0)
• and not(EX/MEM.RegWrite and (EX/MEM.RegisterRd ?
  0)
• and (EX/MEM.RegisterRd ID/EX.RegisterRs) )
• and (MEM/WB.RegisterRd ID/EX.RegisterRs))
  ForwardA 01
• if (MEM/WB.RegWrite
• and (MEM/WB.RegisterRd ? 0)
• and not(EX/MEM.RegWrite and (EX/MEM.RegisterRd ?
  0)
• and (EX/MEM.RegisterRd ID/EX.RegisterRt) )
• and (MEM/WB.RegisterRd ID/EX.RegisterRt))
  ForwardB 01

14
See PH Fig. 6.32 3rd Ed or 4.56 4th Ed

• The datapath modified to resolve hazards via
  forwarding.

15
The Snapshots of Our Example Through Forwarding
16
Some conventions

• The bold lines are those active in a clock cycle.
• The italicized register numbers in color with a
  red circle indicate a hazard.
• The forwarding unit is highlighted by shading it
  when it is forwarding data to the ALU.
• The in the place of operands means that their
  identity is information not needed by the stage.

17
See PH Fig. 6.14.11 3rd Ed CD (For more practice
section)

• Clock cycles 3 of the instruction sequence.

18
See PH Fig. 6.14.11 3rd Ed CD (For more practice
section)

• Clock cycles 4 of the instruction sequence.

19
See PH Fig. 6.14.12 3rd Ed CD (For more practice
section)

• Clock cycles 5 of the instruction sequence.

20
See PH Fig. 6.14.12 3rd Ed CD (For more practice
section)

• Clock cycles 6 of the instruction sequence.

21
Hazards and Stalls
22
See PH Fig. 6.34 3rd Ed or 4.58 4th Ed

• A pipelined sequence of instructions.

23
Bubble

• The way stalls are really inserted into the
  pipeline

24
See PH Fig. 6.35 3rd Ed or 4.59 4th Ed
The way stalls are really inserted into the
pipeline (Another View)
25
Forwarding with Load and Stores

• The problem
• The solution

26
A Hazard Detection Unit
In the ID stage, the following should be checked
by the hazard detection unit, so it can insert
the stall between a load and its use. if
(ID/EX.MemRead and ((ID/EX.RegisterRt
IF/ID.RegisterRs) or (ID/EX.RegisterRt
IF/ID.RegisterRt)) stall the pipeline
27
Pipelined control overview, showing the two
multiplexors for forwarding, the hazard detection
unit, and the forwarding unit.
28
Snapshots of the running example through the
pipeline
29
See PH Fig. 6.14.14 3rd Ed CD (For more practice
section)

• Clock cycles 2 of the instruction sequence in the
  example.

30
See PH Fig. 6.14.14 3rd Ed CD (For more practice
section)

• Clock cycles 3 of the instruction sequence in the
  example.

31
See PH Fig. 6.14.15 3rd Ed CD (For more practice
section)

• Clock cycles 4 of the instruction sequence in the
  example.

32
See PH Fig. 6.14.15 3rd Ed CD (For more practice
section)

• Clock cycles 5 of the instruction sequence in the
  example.

33
See PH Fig. 6.14.16 3rd Ed CD (For more practice
section)

• Clock cycles 6 of the instruction sequence in the
  example.

34
See PH Fig. 6.14.16 3rd Ed CD (For more practice
section)

• Clock cycles 7 of the instruction sequence in the
  example.
• (note the forwarding of 4)

35
Branch Hazards and Handling

• Branch hazards
• Branch hazard handling methods
• Static
• Dynamic