Recap Pipeline Hazards

1
(Recap)Pipeline Hazards
2
Data Hazard on r1
Time (clock cycles)
3
Data Hazards

• Read After Write (RAW) InstrJ tries to read
  operand before InstrI writes it
• Caused by a Dependence (in compiler
  nomenclature). This hazard results from an
  actual need for communication.

I add r1,r2,r3 J sub r4,r1,r3
4
Data Hazards

• Write After Read (WAR) InstrJ writes operand
  before InstrI reads it
• Called an anti-dependence by compiler
  writers.This results from reuse of the name
  r1.
• Cant happen in MIPS 5 stage pipeline because
• All instructions take 5 stages, and
• Reads are always in stage 2, and
• Writes are always in stage 5

5
Data Hazards

• Write After Write (WAW) InstrJ writes operand
  before InstrI writes it.
• Output dependence by compiler writers
• This also results from the reuse of name r1.
• Cant happen in MIPS 5 stage pipeline because
• All instructions take 5 stages, and
• Writes are always in stage 5
• Will see WAR and WAW in complicated pipelines

6
Stall One Way to Fix a Data Hazard
Can fix data hazard by waiting stall but
affects throughput
add r1,r2,r3
I n s t r. O r d e r
7
Solution Data Forwarding
Time (clock cycles)
8
HW Change for Forwarding
MEM/WR
ID/EX
EX/MEM
NextPC
mux
Registers
Data Memory
mux
mux
Immediate
9
Yet Another Complication!

• Another potential data hazard can occur when
  there is a conflict between the result of the WB
  stage instruction and the MEM stage instruction
  which should be forwarded?

I n s t r. O r d e r
add r1,r1,r2
add r1,r1,r3
add r1,r1,r4
10
Data Hazard Even with Forwarding
Time (clock cycles)
lw r1, 0(r2)
I n s t r. O r d e r
ALU
Reg
Reg
Mem
IF
Bubble
sub r4,r1,r6
Reg
IF
Bubble
and r6,r1,r7
IF
Bubble
or r8,r1,r9
11
Forwarding with Load-use Data Hazards
lw r1,100(r2)
I n s t r. O r d e r
sub r4,r1,r5
sub r4,r1,r5
12
Software Scheduling
Try producing fast code for a b c d e
f assuming a, b, c, d ,e, and f in memory.
Slow code LW Rb,b LW Rc,c ADD
Ra,Rb,Rc SW a,Ra LW Re,e LW
Rf,f SUB Rd,Re,Rf SW d,Rd

• Fast code
• LW Rb,b
• LW Rc,c
• LW Re,e
• ADD Ra,Rb,Rc
• LW Rf,f
• SW a,Ra
• SUB Rd,Re,Rf
• SW d,Rd

Compiler optimizes for performance. Hardware
checks for safety.