Pipelining, ILP and Data Dependencies

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Pipelining, ILP and Data Dependencies

• Susmit Biswas

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Pipelining

• In computing, a pipeline is a set of data
  processing elements connected in series, so that
  the output of one element is the input of the
  next one.
• The elements of a pipeline are often executed in
  parallel or in time-sliced fashion in that case,
  some amount of buffer storage is often inserted
  between elements.
• - Wikipedia

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Stages in Pipeline Classic 5 Stage

• Instruction Fetch
• From Instruction Cache
• Instruction Decode
• Identify op-code and operand read from register
• Execute
• Functional unit
• Memory Access
• Read or write to memory (ld/st)
• Writeback
• Writing to Register

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MIPS CPU Unpipelined
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Pipeline Registers
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Advantages and Disadvantages

• Advantages of pipelining
• cycle time reduced
• increased instruction bandwidth
• Advantages of not pipelining
• The processor executes only a single instruction
  at a time.
• This prevents branch delays
• The design is simpler and cheaper to manufacture.
  
• Slightly lower latency in non-pipelined
  processor.
• Extra flip-flops must be added to the data path
  of a pipelined processor.
• Easier to predict performance

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ILP

• Static and dynamic scheduling
• Static does not get so information
• Rearrangement of instructions to obtain
  parallelism
• Dynamic has high overhead
• Out of order execution

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Hazards

• Structural Hazards
• Data Hazards
• Data Dependence
• Name Dependence
• Anti-dependence
• Output dependence
• Control Hazard

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Data Hazard

• SUB r3,r4 -gt r10
• AND r10,r3 -gt r11

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Data Dependencies
No Scheduling Static Scheduling Dynamic Scheduling
Stall

• ADD R1, R2, R3
• DIV R8, R1, R3
• ADD R3, R4, R5
• ADD R3, R6, R7

• Rearrangement
• Remove Dependence

RAW
WAR
Out of order Execution
WAW
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Data Dependencies
Stall

• ADD R1, R2, R3
• DIV R8, R1, R3
• ADD R3, R4, R5
• ADD R3, R6, R7

RAW

• Use more registers

No Scheduling Static Scheduling Dynamic Scheduling
WAR
WAW

• Scoreboard stalls
• Register renaming

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Questions?

• Wikipedia ?
• Computer Architecture A Quantitative Approach,
  Third Edition
• by John L. Hennessy, David A. Patterson
• http//www.altera.com/products/software/products/q
  uartus2web/sof-quarwebmain.html
• https//www.altera.com/support/licensing/free_soft
  ware/lic-q2web.jsp

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Structural Hazard

• A structural hazard occurs when a part of the
  processor's hardware is needed by two or more
  instructions at the same time.
• Multiple cycle execution in 1 functional unit
• Same unit shared between two stages

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Structural Hazard Example

• Unified instruction and data memory

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Control Hazard

• Branching hazards (also known as control hazards)
  occur when the pipelined processor executes
  branch instruction.
• In such a case, the processor cannot tell in
  advance whether it should process the next
  instruction (when it may instead have to move to
  a distant instruction).
• This can result in the processor doing unwanted
  actions.

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Example

•     add r1, r2, r3
• j   l1         // Jump to (label) l1
• sub r2, r3, r0 l1
• xor r3, r0, r1 ori r1, r2, 10
• Cycle IF ID EX MA WB
• 1 add   
• 2 j add  
• 3 sub j add   branch resolved
• 4 xor sub j add
• 5 ori xor sub j add

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Cont.

• Cycle IF ID EX MA WB
• 1 add   
• 2 j add  
• 3 sub j add   
• 4 xor j nop add 
• 5 ori xor j nop add

Stall
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Solution Prediction

• Branch Prediction
• Global
• Local
• Hybrid

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Data Hazard

• RAW
• WAR
• WAW

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Eliminating Hazards

• Stall
• Forwarding
• Register Renaming

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Another Example
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Sharing Cycle

• Writing in 1st haft and reading in 2nd

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Stall

• Insert bubble in the pipeline

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Forwarding
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Register Renaming

• In out-of-order processor
• Reservation station based or Tomasulo based
  architecture
• Beyond scope of todays discussion