2005 Symposium on VLSI Circuits

1
2005 Symposium on VLSI Circuits
AdCom - 2/6/05 Bill Bidermann
2
Agenda

• Review of 2004 Symposium
• Best Student Paper
• Calendar
• Financials
• Technical Program Committee
• Invited Papers
• Rump Sessions
• Short Course

3
Review of 2004 Symposia

• Circuits Symposium
• Registration 411 (vs. 361 in 2002)
• Circuits Short Course 99 (vs. 107 in 2002)
• Paper submissions
• 108 accepted of 329 submissions 33 accept rate
• vs. 84 of 193 in 2002
• Best Student Paper Award (will continue in US,
  Japan eval)
• Technology Symposium
• Registration 650 (vs. 548 in 2002)
• Technology Short Course 258 (vs. 209 in 2002)
• Paper submissions
• 96 papers accepted of 304 submissions 32
  accept rate
• vs. 84 of 232 accepted in 2002
• All Electronic Presentations
• Produced CD ROM
• Media Kit circulated

4
Review of 2004 Symposium
5
Best Student Paper Award

• Award Established/started in 2004 Symposium at
  Hawaii
• 500 Cash, Travel
  Registration to the Next Symposium, a Plaque
  (2000 Estimated in the Symposium Budget)
• Selection Based upon the Quality of the
  Written Paper and the Presentation
• Pre-Selection of the Best Student Papers Based
  based upon the TPC Scores
• Student must be 1st Author Joint
  University/Industry Papers are Eligible.
• From the Technical Program Committee, a
  Voluntary Selection Committee will be
• Formed (Members Jointly
  from the NAE JFE with an Appointed Sub-
• Committee Chair)
• Best Student Paper Selection Committee Members
  must NOT be Co-Authors on
• ANY of the Papers
• The Best Student Paper Selection Committee
  must attend all of the paper
• presentations and
  Provide Scoring (except for Conflicts).
• The Technical Program Chair will Review the
  Scoring and Make a Recommendation to the Joint
  Executive Committee at the Subsequent IEDM
• Executive Meeting
• The Award is Presented at the Next Symposium

6
Calendar

• 1st Program Committee Meeting 8/26/04
• 2nd Program Committee Meeting (Telecom) 12/03/04
• IEDM, December 13th (Monday) through December
  15th (Wednesday)
• San Francisco, CA
• Executive Committee Meeting 12/14/04
• Paper Submission Deadline 1/7/05
• Papers Distributed and Received 1/14/05
• Ratings Due to Phyllis Mahoney 2/3/05
• NAE Paper Selection (San Francisco, CA) 2/10/05
• ISSCC, February 6th (Monday) through February 9th
  (Wednesday)
• ISSCC Short Course on February 10th (Thursday),
  San Francisco, CA
• Final JFE Paper Selection Meeting 2/18/05
• VLSI Symposium Short Course 6/15/05
• VLSI Symposium in Kyoto 6/16 - 6/18/05

7
Financials

• 10K Surplus for 2004
• Complete audit next month
• 2005 Symposia hosted in Japan
• Fees set with lower dollar
• Short Course registration very topic dependent

8
Technical Program Committee

• Technical Chair Stephen Kosonocky
• Secretary
• Ajith Amerasekera, Texas Instruments
• Rump Sessions
• Ken Yang, UCLA
• Publicity and Publications
• Wai Lee, Texas Instruments
• Best Student Paper Award Committee
• Chairman, Ching-Te Chuang, IBM

9
2005 NAE TPC

• Ajith Amerasekera
• TI
• Asad Abidi
• UCLA
• Bin Zhao
• Skyworks Solutions
• Borivoje Nikolic
• UCBerkeley
• Bruce Gieseke
• AMD
• Ching-Te Chuang
• IBM
• Corrado Villa
• ST Micro
• Georg Braun
• Infineon
• Greg Taylor
• Intel
• Harry Pon

• Kaushik Roy
• Purdue
• Ken Yang
• UCLA
• Kevin Nowka
• IBM
• Margaret Huang
• Freescale
• Per Larsson-Edefors
• Chalmers Unv.
• Peter Kinget
• Columbia
• Sreedhar Natarajan
• ATMOS
• Stephen Kosonocky
• IBM
• Steven Butler
• AMD
• Travis Blalock

10
Invited Talks

• Prospects and Challenges of Flash Memory for
  Mobile Consumer Applications
• Dr. Yun-Seung Shin Samsung
• Robots will drive IC Technology and Industry
• Dr. Hiroaki Kitano
• Sony
• Ultra Wide Band (UWB)
• John McCorkle
• Freescale
• Space Electronics
• Mohammad Mojarradi
• NASA - JPL

11
Rump Sessions
Organizers NAE (Circuit) C.K. Ken Yang,
UCLA JFE (Circuit) Mamoru Ugajin, NTT Low Power
Design Process Puzzle or Design Dilemma NAE Jim
Farrell, AMD JFE Yukihito Oowaki, Toshiba
Semiconductor Digitizing the radio to the
antenna will radios still need analog in
2010? NAE Margaret Huang, Freescale JFE Akira
Matsuzawa, Tokyo Institute of Technology The
Roadblock to the TeraBit (1012 bits) Memory Era
Technology or Design? NAE Harry Pon, Intel
JFE Tomoyuki Ishii, Hitachi Joint
Rump Variability has stopped scaling Who will
conquer the issues of variability? JFE Ckts
Koichiro Ishibashi, Renesas Technology JFE
Technology Hiroo Masuda, STARC, NAE Ckts
Borivoje Nikolic, UC Berkeley NAE Technology
Rajat Rakkhit, Cypress
12
Short Course

• Multi-Ghz clocking technologies for
  microprocessors
• Organizers
• NAE Vivek De (Intel)
• JFE Makoto Nagata
• Basics of clock generation/distribution
• Keng Wong (Intel)
• Toward 10GHz clock generation/distribution
• Phillip Restle (IBM)
• PLL's, VCO's, DLL's and delay elements
• Nasser Kurd (Intel)
• On-chip skew adjustment techniques
• Tetsuya Higuchi (AIST, Japan)
• Techniques for synchronizing multiple clock
  domains
• Masayuki Mizuno (NEC)
• Clocking for low-power/low-voltage designs
• Michio Komoda (Renesas)