Nanometer VLSI Physical Design for Manufacturability and Reliability

1
Nanometer VLSI Physical Design for
Manufacturability and Reliability
Ph.D. Proposal May 3rd, 2007

• Minsik Cho
• Dept. of Electrical and Computer Engineering
• The University of Texas at Austin
• thyeros_at_cerc.utexas.edu

2
Outline

• Introduction
• Introduction VLSI Routing and DFM
• Manufacturability-driven routing
• BoxRouter for global routing framework
• Wire density-driven global routing for CMP
  variation and timing
• TROY Track routing with yield-driven wire
  planning
• Litho-driven detailed routing
• Conclusion

3
Modern VLSI Design

• VLSI Physical Design
• Last design step before manufacturing
• Big impact on performance, power, noise, and
  manufacturability
• Different designs lead to different
  manufacturability.
• Better yield and low cost from better
  manufacturability

4
Routing in VLSI Physical Design
a
c
a
Placement
b
Routing
Routing
a
d
d
b
a
c
c
5
90/65/45nm DFM Issues
2007
2005
2006
45 nm
65 nm
90 nm
130nm
Courtesy Cadence, 2007

• DFM(Y) Design for Manufacturability (Yield)
• Chemical-mechanical polishing (CMP), particle
  defects (CAA), and lithography are key
  contributors to DFM.
• - Dr. Scheffer (Cadence), Dr.
  Domic (VP, Synopsys), Dr. Puri (IBM)

6
Sub-wavelength Lithography

• Minimum feature size is scaling down faster than
  wavelength.
• Nanolithography (e.g., Nanoimprint, E-BEAM, EUVL)
  are not mature/economical for mass production
  yet.
• It looks like optical lithography with help of
  immersion and RET will be a work horse for next
  510 years.

7
RET Optical Proximity Correction (OPC)
Original mask
Courtesy Intel, 2006

• Insufficient critical dimension causes not only
  circuit failure but also timing degradation.
• Additional polygons are added to enhance
  resolution.
• Need to run computationally expensive OPC tools.
• Mask data volume is increased due to more
  features.

8
Chemical-mechanical Polishing (CMP)
Topography variation translated into focus
variation for lines which results in width
variation

• CMP (Chemical-Mechanical Polishing)
• Key multilevel metallization technique for copper
  interconnect
• CMP (topography) variation
• Performance degradation due to increased wire
  resistance
• Depth of focus issues due to non-uniform surface
• Systematic variation due to non-uniform metal
  density distribution
• Dummy fill increases mask volume and coupling
  capacitance.

9
Random Defects
open
short

• Two kinds of random defects
• Open defects due to missing material
• Short defects due to additional material
• Technology scaling makes a design more vulnerable
  to random defects.
• More (smaller) defects become smaller than
  minimum feature size.

10
Yield Loss Projection Scary
Critical Area
CMP Lithography
Courtesy IBS
Need to do something for CMP, Critical Area, and
Lithography
11
Outline

• Introduction
• Introduction to DFM and VLSI Routing
• Manufacturability-driven routing
• BoxRouter for global routing framework
• Wire density-driven global routing for CMP
  variation and timing
• TROY Track routing with yield-driven wire
  planning
• Litho-driven detailed routing
• Conclusion

12
Rule-based Approach
Cong, ICCAD06

• Conventional approach to separate design from
  manufacturing RULES
• Rules are starting running out of steam from 65nm
• Exploding number of rules
• VERY complicated rules (Rule book for 90nm has
  600 pages)
• Not accurate any more

13
Model-based Approach
Lithography enhancement
CMP variation optimization
Critical area minimization

• The most effective VLSI design step for DFM
• Clearer picture about the final design layout
  than any other steps
• Those DFM issues are tightly coupled with wires.
• Significant design flexibility for wiring
• CMP variation optimization
• Minimum effective window (20x20µm2) and global
  effect
• Global routing plans approximate routing path.
• Critical area minimization
• Adjacent parallel wires contribute majority of
  critical area.
• Track router has decent flexibility in
  optimization with wire adjacency information.
• Lithography enhancement
• Effective windows (1µm2 ) and local effect
• Detailed router performs localized connection
  between pins/wires.

14
Outline

• Introduction
• Introduction to DFM and VLSI Routing
• Manufacturability-driven routing
• BoxRouter for global routing framework
• Wire density-driven global routing for CMP
  variation and timing
• TROY Track routing with yield-driven wire
  planning
• Litho-driven detailed routing
• Conclusion

15
BoxRouter Overview

• Incremental Box Expansion
• From the most congested region
• Progressive ILP
• adaptive maze routing
• PostRouting
• Negotiation-based approach
• 2nd place in ISPD07 routing contest

Global routing cell (G-cell)
16
Overall Flow of BoxRouter
Minimum Steiner Tree Net Decomposition (Node
shifting)
PreRouting Initial Box
BoxRouting
2D Global Routing
Robust Negotiation-based ReRouting (Topology-aware
wire ripup)
Greedy Wirelength/Via Minimization
Via/Blockage-aware Layer Assignment (Progressive
via/blockage-aware ILP)
Greedy Wirelength/Via Minimization
17
PreRouting

• Preroute as many flat wires as possible
• 60 of wirelength can be prerouted
• Benefits
• Overall congestion captured
• Runtime improved
• Starting Box of BoxRouting

18
BoxRouting in Action
ILP returns the optimal (high quality) solution.
However, in general, it is believed to be
unacceptably slow. Is runtime OK?
routing cap. constraint
YES!
solution constraint
19
Progressive ILP with Box Expansion

• Progressive ILP
• Incorporate the solution from inner boxes
• Solve it between two consecutive boxes

20
Proposed ILP vs. Conventional ILP
max
s.t

• Conventional ILP formulation
• Minimize max overflow
• Overflow should be fixed by maze router

• Proposed ILP formulation
• Maximize routed nets (min. total overflow)
• Unrouted wire should handled by maze router

Yang ICCAD01
21
Proposed ILP vs. Conventional ILP
GNU Linear Programming Kit 4.10, Industrial
circuit (7mm x 7mm)
22
Via/Blockage-Aware Layer Assignment

• Layer assignment follows 2D global routing.
• Most of advanced technology have multiple layers.
• Via provides electrical connection between wires
  in different layers.
• Via has higher probability of failure (e.g.,
  redundant via)

23
Layer Assignment Example

• The number of vias is decided by layer assignment
  and blockages

24
Via/Blockage-aware Layer Assignment
for every steiner point s of each net i
min
assigned only once
compute layer
get top/bottom layer of steiner point
pins on M1
routing cap. constraint

• Unassigned wires will be picked up by simple maze
  routing which only shuttles between layers.

25
Routability Improvement
0 overflow

• Only BoxRouter completes ISPD98 IBM benchmark.

26
Wirelength Improvement

• BoxRouter shows the minimum wirelength.

27
Outline

• Introduction
• Introduction to DFM and VLSI Routing
• Manufacturability-driven routing
• BoxRouter for global routing framework
• Wire density-driven global routing for CMP
  variation and timing
• TROY Track routing with yield-driven wire
  planning
• Litho-driven detailed routing
• Conclusion

28
Predictive CMP Model For Global Routing

• Global routing is the first routing planning
  phase
• Predictive and fast CMP model is required

29
Predictive CMP Model (Cu Thickness)

• Cu Thickness is systematically dependent on metal
  density

30
Predictive CMP Model (Metal Density)

• Metal density Wire density Dummy fill density
• Look-up table for fast computation

31
Global Routing Flow With Predictive CMP Model
Dummy Fill Density From Lookup Table
Wire Density
Metal Density Wire Density Dummy Fill Density
Cu Thickness
Cu Thickness
Predictive CMP Model for Global Routing

• Predictive CMP Model guides global router
• More uniform wire distribution
• Consider metal blockages (power/ground rail, IPs)

32
CMP Variation Improvement

• On average 7.5 reduction
• Up to 10.1 reduction

33
Outline

• Introduction
• Introduction to DFM and VLSI Routing
• Manufacturability-driven routing
• BoxRouter for global routing framework
• Wire density-driven global routing for CMP
  variation and timing
• TROY Track routing with yield-driven wire
  planning
• Litho-driven detailed routing
• Conclusion

34
Critical Area For Yield
C
A
B

• Random defect can cause open/short defect
• Wire planning for critical area reduction
• Defect size distribution
• Chance of getting larger defect decreases rapidly
  TCAD85
• Concurrent optimization for open/short defect
• Larger wire width for open, but larger spacing
  for short defect
• Limited chip area

35
TROY Overview

• TROY is a track router for yield enhancement
• Find initial solution through interval packing
• Wire ordering to minimize overlapped wirelength
  between neighbors
• Wire sizing/spacing to minimize critical areas
• Contribution of TROY
• The impact detailed wirelength on critical area
  is considered
• SOCP provides globally optimal wire size/spacing
  for entire layer for the given objective in near
  linear time

36
Math for Critical Area
Defect size distribution r 3
Critical are due to open defect
Critical are due to short defect
Probability of failure (POF) for open/short
defects
Approximated POF

• POF is convex function.
• Global optimal can be found, but POF is
  complicated.
• Approximated POF is also convex, but easy enough
  to enable SOCP.

37
Yield-Driven Track Routing
POF for short
POF for open

• Integer nonlinear programming
• Extremely hard to solve
• Integer variable for the wire order (which is
  above/below which)
• Key observation
• Objective is convex, which can be further written
  in rotated conic form if the approximated POF is
  adopted.
• If all integer values are given, efficiently
  solvable by interior point method.

38
TROY Strategy
Solved by finding minimum Hamiltonian path
Integer nonlinear programming
Wire sizing/spacing
Second order conic programming

• A class of convex programming researched from
  late 90s
• Guaranteed to find the global optimum
• As efficiently solvable by primal-dual interior
  point algorithm as LP

39
Yield Improvement

• Monte-Carlo simulation with 10K defects
• On average 18 reduction in yield loss, up to
  30
• 2.2 improvement loss with discrete wire width

40
Outline

• Introduction
• Introduction to DFM and VLSI Routing
• Manufacturability-driven routing
• BoxRouter for global routing framework
• Wire density-driven global routing for CMP
  variation and timing
• TROY Track routing with yield-driven wire
  planning
• Litho-driven detailed routing
• Conclusion

41
Litho-driven Detailed Routing
Our simulator
PROLITH

• Future work to round off manufacturability-driven
  routing
• Fast litho-simulator to guide detailed router
• Validated with PROLITH (orders of 106 faster)
• Should consider OPC into account
• Never considered in routing research so far

42
Conclusion

• State-of-the-art router, BoxRouter is developed.
• Three key contributors to VLSI Manufacturability
  are addressed in routing.
• Global routing for CMP variation optimization
  along with timing improvement
• Track routing for critical area minimization
• Detailed routing for lithography enhancement
  (future work)

43
Publications

• 2005
• Minsik Cho, Suhail Ahmed and David Z. Pan , 
  "TACO Temperature Aware Clock-tree
  Optimization",  Proc. ACM/IEEE Int'l Conference
  on Computer-Aided Design (ICCAD), Nov, 2005
• 2006
• Minsik Cho, Hongjoong Shin and David Z. Pan , 
  "Fast Susbstrate Noise-Aware Floorplanning with
  Preference Directed Graph for Mixed-Signal
  SOCs",  Proc. Asian and South Pacific Design
  Automation Conference (ASPDAC), January, 2006
  (Nominated for Best Paper Award)
• Minsik Cho and David Z. Pan ,  "PEAKASO
  Peak-Temperature Aware Scan-Vector
  Optimization",  Proc. IEEE VLSI Test Symposium
  (VTS), April, 2006
• Minsik Cho and David Z. Pan ,  "BoxRouter A New
  Global Router Based on Box Expansion and
  Progressive ILP",  Proc. Design Automation
  Conference (DAC), July, 2006 (Nominated for Best
  Paper Award)
• Minsik Cho, Hua Xiang, Ruchir Puri and David Z.
  Pan ,  "Wire Density Driven Global Routing for
  CMP Variation and Timing",  Proc. ACM/IEEE Int'l
  Conference on Computer-Aided Design (ICCAD),
  November, 2006
• Minsik Cho, Hongjoong Shin and David Z. Pan , 
  "Fast Susbstrate Noise-Aware Floorplanning with
  Preference Directed Graph for Mixed-Signal
  SOCs",  IEEE Transactions on VLSI (TVLSI), under
  review
• Minsik Cho and David Z. Pan ,  "BoxRouter A New
  Global Router Based on Box Expansion and
  Progressive ILP",  IEEE Transactions on
  Computer-Aided Design of Integrated Circuits and
  Systems (TCAD), accepted for publication
• 2007
• Minsik Cho, Hua Xiang, Ruchir Puri and David Z.
  Pan ,  "TROY Track Router with Yield-driven Wire
  Planning",  Proc. Design Automation Conference
  (DAC), June, 2007
• Minsik Cho, Katrina Lu, Kun Yuan and David Z. Pan
  ,  Architecture and Implementation of a Robust
  Global Router for Ultimate Routability",  Proc.
  ACM/IEEE Int'l Conference on Computer-Aided
  Design (ICCAD), submitted for review

44
BACK UP SLIDES
45
Sub-wavelength Lithography
Courtesy Intel, 2006

• Minimum feature size is scaling down faster than
  wavelength.
• Nanolithography (e.g., Nanoimprint, E-BEAM, EUVL)
  are not mature/economical for mass production
  yet.
• It looks like optical lithography with help of
  immersion and RET will be a work horse for next
  510 years.

46
Optical Lithography System
47
RET Phase Shift Mask
One wide feature will be printed
Two features will be printed as designed
48
Routing in VLSI Physical Design
a
c
a
Placement
b
Routing
Routing
a
d
d
b
a
c
c
49
Non-Trivial Synergistic Optimization Redundant
Via and Litho

• Contact Redundancy does
• not come for free
• Requires Synergistic
• Optimizations

L.Liebmann, SPIE06
50
Rule-based Approach
End of line spacing rules

• Conventional approach to separate design from
  manufacturing RULES
• Rules are starting running out of steam from 65nm
• Exploding number of rules
• VERY complicated rules (Rule book for 90nm has
  600 pages)
• Not accurate any more

51
Chemical-mechanical Polishing (CMP)
Courtesy TSMC

• CMP (Chemical-Mechanical Polishing)
• Key multilevel metallization technique for copper
  interconnect

52
CMP (Topography) Variation
Copper Material
High metal density
Low metal density

• CMP Variation
• Performance degradation due to increase
  resistance
• Depth of focus issues due to non-uniform surface
• Systematic variation due to non-uniform metal
  density distribution
• Dummy fill increases mask volume and coupling
  capacitance.

53
Random Defect and Critical Area
C
A
B
54
Motivation for Box Expansion
c
a
c
b
d
a
b
d

• Different resource management for wires
  in/outside of box
• Box Expansion pushes/diffuses congestion outwards
  progressively

55
Negotiation-based ReRouting
vC
vD
x
x

• Negotiation-based approach
• Enhance routing path by rerouting wires
• The congestion history is maintained to avoid
  previously congested regions.
• Multiple iterations

56
Via-aware Layer Assignment
min
s.t
57
Via-aware Layer Assignment
for every steiner point s of each net i
min
s.t
assigned only once
compute layer
get top/bottom layer of steiner point
pins on M1
routing cap. constraint

• The proposed ILP formulation finds layer
  assignment with minimum number of vias.

58
Via/Blockage-aware Layer Assignment
min

• Unassigned wires will be picked up by simple maze
  routing which only shuttles between layers.

59
Wire Density and Timing

• Coupling capacitance becomes dominant factor in
  timing.
• 60 of total capacitance below 180nm node
• Rapidly increase due to higher aspect (W/L) ratio
• Less coupling capacitance
• With less number of wires within a given region
• Lower wire density will reduce coupling
  capacitance.
• In the first order, coupling capacitance is
  linearly proportional to wire density.

60
Wire Density Driven Global Routing Overview

• Modify the cost function of maze router in
  ReRouting
• Add wire density term as a cost factor
• Keep congestion term
• How to smartly guide the maze router?

• Reduce the wire density around timing critical
  nets
• Less coupling capacitance
• Timing sensitivity map

Timing

• Reduce the wire density of selected dense regions
• Predictive CMP model

CMP
61
Timing Sensitivity Map
S
R1R2
C
D
T To (R1R2 ) C

• Lower downstream capacitance improves timing
• Higher wire density near the driver is better
  than higher wire density near the critical sink

62
Recap Proposed Global Routing
Timing
Timing Sensitivity Map
Discourage maze router from passing a sensitive
or dense G-cell
CMP
Predictive CMP Model
63
Timing Improvement

• On average 7 reduction
• Up to 10 reduction

64
Timing Sensitivity Map

• Each global routing cell has different impact on
  timing
• Whether it is closer to the timing critical sink
• Whether there are more timing critical nets inside

65
Notations

• Wire spacing
• Adjacent wires
• Overlapped wirelength
• Adjacent and overlapped wirelength
• Preferred location for minimum detailed wirelength

66
Second Order Conic Programming

• A class of convex programming
• Minimizing a linear objective over the
  intersection of an affine linear manifold with
  the Cartesian product of second-order cones
• Guaranteed to find the global optimum
• Efficiently solvable by primal-dual interior
  point algorithm
• Constant Hessian
• Self-duality of quadratic cones
• Nesterov-Todd (1997) direction
• Mehrotra type predictor-corrector

Geometrical illustration of conic constraint in 3D
67
TROY Strategy
Integer nonlinear programming
Wire sizing/spacing
Second order conic programming
68
Wire Ordering
Initial solution from interval packing
Solved by finding minimum Hamiltonian path
69
Wire Spacing/Sizing

• When wire order is fixed
• Two auxiliary variables are introduced
• Two rotated quadratic conic constraints are added
• SOCP is solved for one entire layer
• Provides globally optimal wire width and spacing