ZiLOG80

1
ZiLOG80
Calcolatori Elettronici
Bartolomeo Bajic
2
A
F
F
A
I
W
Z
W
Z
R
B
C
B
C
Flags 8 bit
D
E
D
E
H
L
H
L
S
Sign
Z
Zero
-
-
I
X
H
Half-Carry
I
Y
-
-
S
P
P/V
Parity/overfl.
N
Negate
P
C
C
Carry
Memoria Interna allo Z80
3
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
M1
T5
Z80
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
T1
T2
T3
T4
T5
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
4
LD B,C
T1
T2
T3
T4
T5
M1
T1
Opcode Fetch
M1
T2
T3
T4
T5
ADD A,(HL)
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
T5
T1
T2
T3
Opcode Fetch
T4
M1
T5
M1
JP nn
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
M1
T5
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
T1
T2
T3
T4
T5
PUSH HL
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
M1
T5
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
T1
T2
T3
T4
T5
Parte comune a tutte le istruzioni
overlap
overlap
5
T1
T2
T3
T4
M1
T5
LD B,C
Mp attende byte su DATA BUS alzando impedenza
T1
T2
T3
Opcode Fetch
T4
T5
M1
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
6
LD B,C
T1
T2
T3
T4
M1
T5
La memoria e lenta! ...incremento PC...
T1
T2
T3
Opcode Fetch
T4
T5
M1
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
7
LD B,C
T1
T2
T3
T4
M1
T5
Istruzione da 1 byte in IR, Refresh memorie
dinamiche
T1
T2
T3
Opcode Fetch
T4
T5
M1
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
DATA BUS 8 Bit
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
8
LD B,C
T1
T2
T3
T4
M1
T5
registri B e C non sono in comunicazione diretta
T1
T2
T3
Opcode Fetch
T4
T5
M1
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
9
LD B,C
T1
T2
T3
T4
M1
T5
Pipelining! Comincia gia lettura istruzione
successiva
T1
T2
T3
Opcode Fetch
T4
T5
M1
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
10
T1
T2
T3
T4
M2
T1
T2
T3...
T5
ADD A,(HL)
Opcode Fetch come per LD B,C
T1
T2
T3
Opcode Fetch
T4
M1
T5
M1
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
11
ADD A,(HL)
T1
T2
T3
T4
M2
T1
T2
T5
T3...
Scarico HL invece di PC sullADDRESS BUS
T1
T2
T3
Opcode Fetch
T4
T5
M1
M1
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
DATA BUS 8 Bit
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
12
ADD A,(HL)
T1
T2
T3
T4
M2
T1
T2
T5
T3...
Carico contenuto di (HL) in Temp
T1
T2
T3
Opcode Fetch
T4
T5
M1
M1
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
DATA BUS 8 Bit
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
13
ADD A,(HL)
T1
T2
T3
T4
M2
T5
T1
T2
T3...
M2 attende, ma parte Opcode F. seguente
T1
T2
T3
Opcode Fetch
T4
T5
M1
M1
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
14
ADD A,(HL)
T1
T2
T3
T4
M2
T5
T2
T1
T3...
In T5 termina ADD, coincide con M1 T2
T1
T2
T3
Opcode Fetch
T4
T5
M1
M1
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
15
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
M1
T5
JP nn
W e Z sono registri ombra
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
T1
T2
T3...
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
DATA BUS 8 Bit
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
16
JP nn
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
M1
T5
Secondo byte in W
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
T1
T2
T3...
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
DATA BUS 8 Bit
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
17
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
M1
T5
JP nn
Scarico WZ sull ADDRESS BUS
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
T1
T2
T3...
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
18
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
M1
T5
JP nn
Incremento WZ e carico in PC
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
T1
T2
T3...
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
19
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
T5
PUSH HL
Stack Pointer tipo FIFO
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
T1
T2...
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
-1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
20
PUSH HL
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
T5
Scrivo High byte in (SP)
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
T1
T2...
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
-1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
21
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
T5
PUSH HL
Decremento ancora SP
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
T1
T2...
Buffer
INTERNAL
DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
-1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
22
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
T5
PUSH HL
Tengo tutto sui Buffer
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
T1
T2...
Buffer
INTERNAL
DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
Z
R
Flags
W
IR Instruction Register
S
Sign
B
C
C
B
Temp
Temp A
Z
Zero
1
D
E
E
D
-
-
H
L
L
H
Half-Carry
H
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
-1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
23
T1
T2
T3
T4
M2
T1
T2
T4
T5
T5
T3
PUSH HL
Scarico Low byte in (SP)
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
T1
T2...
Buffer
DATABUS 8 bit
INTERNAL
d displacement byte
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
-1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
24
T1
T2
T3
T4
M2
T1
T2
T3
T4
T5
T5
PUSH HL
T1
T2
T3
Opcode Fetch
T4
M3
T5
M1
Buffer
INTERNAL
DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
-1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
25
Routine termina con RETN return from NMI IFF2
IFF1
Gestione INT
0IFF1 PC (SP) 0066HPC
NMI
Esegue listruzione allindirizzo 0066H
INT
Controlla stato IFF1 Interrupt enable Flip-Flop
disabilitato
Ignora INTerrupt
abilitato
Istruzioni collegate EI Enable Interrupt DI
Disable Interrupt IM x Interrupt Mode x
Controlla BUSREQ 0IFF1, 0IFF2
Gestione BUSREQ
attivo
inattivo
Controlla stato di IM x
IM0 Lo Z80 aspetta sul DATA BUS unistruzione
proveniente dalla periferica che lo ha
INTerrotto. Solitamente tale istruzione sara un
RST (restart) o una CALL
IM1 Un segnale di INTerrupt esegue un CALL
0038H In 0038H avremo una routine di Interrupt
Handler
IM2 La modalita piu frequentmente
usata. Lindirizzo formato dal byte sul DATA
BUS (inviato dalla periferica) e dal
byte contenuto nel registro I contiene a sua
volta lindirizzo della sub-routine da eseguire
26
INT in IM2
T
T
T1
T2
TW
TW
T3
T2
T4
T1
Perriferica invia INTerrupt
M
M
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
27
INT in IM2
T
T
T1
T2
TW
TW
T3
T4
T2
T1
Mp attiva M1 e alza impedenza DATA BUS
M
M
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
28
T
T
T1
T2
TW
T3
INT in IM2
TW
T4
T2
T1
Mp attiva IORQ
M
M
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
29
T
T
T1
T2
TW
TW
T3
INT in IM2
T4
T2
T1
Periferica invia low byte di indirizzo
M
M
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
30
T
T
T1
T2
TW
TW
T3
INT in IM2
T1
T2
T4
Mp legge routine di gestione INTerrupt
M
M
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
A
F
F
A
Multiplexer
I
W
Z
W
Z
Flags
R
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
31
T
T
T1
T2
TW
TW
T3
INT in IM2
T2
T1
T4
incrementa WZ e salva in PC
M
M
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
A
F
F
A
Multiplexer
I
W
Z
W
Z
Flags
R
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
32
INTerrupt handler routine
33
Lassembler Z80 usa istruzioni di lunghezza
totale 1,2,3,4 byte
Legge primo byte
II
SI
CB
Istruzione 2 byte
CB II
NO
DD ED FD
Istruzione 2 byte Dati 1,2 byte Deve
leggere il secondo byte per definire istruzione e
quindi lunghezza totale
II II XX XX II II XX II II
SI
NO
II XX XX II XX II
Istruzione 1 byte Dati 1,2
byte Processore sa da subito quanti sono i byte
34
T1
T2
TW
T3
IORQ RD
Vengono utilizzate solo le linee
A0A7 dellADDRESS BUS (256 dispositivi I/O)
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
low
high
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
35
T1
T2
TW
T3
IORQ RD
LIORQ e simile alla lettura della memoria, ma
si attiva IORQ invece di MREQ
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
36
T1
T2
TW
T3
IORQ RD
Viene automaticamente inserito uno stato
TWait. Una periferica lenta puo inserirne altri
ancora.
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
37
T1
T2
TW
T3
Rilasciato WAIT la periferica scrive
IORQ RD
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
Multiplexer
A
I
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
38
T
T
T
T
T
BUSRQ
Una periferica molto veloce e meglio
scriva /legga direttamente in memoria usa BUSREQ
M
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
39
T
T
T
T
T
Nell M seguente, Mp mette alta impedenza DATA,
ADDRESS, CONTROL. Attiva BUSACK
BUSRQ
M
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
40
T
T
T
T
T
Quando la periferica ha finito rilascia
BUSREQ. Il tutto e detto DMA-Direct Memory Access
BUSRQ
M
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
41
T
T
T
T
T
Mp disattiva BUSACK, riprende controllo BUS Se
DMA lunghi, periferica deve fare Refresh
BUSRQ
M
M
Buffer
INTERNAL DATABUS 8 bit
d displacement byte
DATA BUS 8 Bit
A
F
F
A
I
Multiplexer
W
Z
W
Z
R
Flags
IR Instruction Register
S
Sign
B
C
B
C
Temp
Temp A
Z
Zero
1
D
E
D
E
-
-
H
L
H
L
H
Half-Carry
Arithmetic Logic Unit
Instruction Decoder
-
-
high
low
P/V
Parity/overfl.
IX
I
X
N
Negate
high
low
IY
C
Carry
I
Y
Control Logic

S
P
1
ADDRESS BUS 16 bit
P
C
Machine Cycle One
M1
Memory Request MREQ
Buffer
ADDRESS
BUS 16 bit
Input / Output Request
IORQ
Read RD
System Control
Write WR
Refresh RFSH
Halt State HALT
Buffer
Wait WAIT
CPU Control
Interrupt Request
INT
Non-Maskable Interrupt
NMI
Reset RESET
CPU Bus Control
Bus Request BUSRQ
Bus Acknowledge BUSACK
42
RESET