chapter one transparency

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Chapter 9 68HC11 Serial Communication Interface
The 68HC11 Microcontroller
Han-Way Huang
Minnesota State University, Mankato
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Asynchronous Serial Data Communication - Often
used for data communication between a DTE and a
DCE with or without a modem. - DTE stands for
data terminal equipment and can be either a
computer or a terminal. - DCE stands for data
communication equipment. A modem is a DCE. - A
basic data communication link is shown in Figure
9.1.
- there are three kinds of data communication
links 1. simplex link 2. half-duplex link 3.
full-duplex link
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Types of communication links configuration
The RS232 Standard - was the most widely used
physical level interface for data
communication - specifies 25 interchange circuits
for DTE/DCE use - was established in 1960 by
Electronics Industry Association (EIA) - was
revised into RS232C in 1969 - was revised into
RS232D in 1987 - was revised to RS232E in
1992 - there are four aspects electrical,
functional, procedural, and mechanical
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The RS232D Electrical Specifications - the
interface is rated at a signal rate of lt 20
kbps - the signal can transfer correctly within
15 meters - the maximum driver output voltage
(with circuit open) is -25 V to 25 V - the
minimum driver output voltage (loaded output) is
-25 V to -5 V and 5 V to 25 V - the minimum
driver output resistance when power is off is 300
W - the maximum driver output current (short
circuit) is 500 mA - the maximum driver output
slew rate is 30 V/ms - the receiver input
resistance is 3-7 KW - the receiver input voltage
range is -25 V to 25 V - the receiver output is
high when input is open circuit - a voltage more
negative than -3 V at the receiver input is
interpreted as a logic 1 - a voltage more
positive than 3 V at the receiver input is
interpreted as a logic 0
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The EIA-232E Functional Specifications
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EIA-232E Mechanical Specification - Specifies a
25-bit connector - Specifies exact dimensions of
each pin.
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EIA-232E Procedural Specification - define the
sequence of events that occurs during data
transmission - the procedure is easier to
understand by examples Case 1. Two DTEs
connected via a point-to-point link using a modem.
EIA-232 signals involved - signal ground
(GND) - transmitted data (Tx) - received data
(Rx) - request to send (RTS) - clear to send
(CTS) - data set ready (DSR) - data carrier
detect (DCD)
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Sequence of events occurred during data
transmission over dedicated link
Local
Time
Remote
1. DCE asserts DSR
2. DTE asserts RTS
3. DCE asserts CTS
4. DTE starts to send data (to local DCE)
5. DCE sends out a carrier and then the
modulated data
6. DCE asserts DCD
7. DTE waits for arrival of data
8. DCE sends out demodulated received data
9. DEC receives demodulated data
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Case 2. Two DTEs exchange data through a public
phone line
RS232 signals involved - signal ground
(GND) - transmitted data (Tx) - received data
(Rx) - request to send (RTS) - clear to send
(CTS) - data set ready (DSR) - data carrier
detect (DCD) - data terminal ready (DTR) -
ring indicator (RING)
- The signal DTR is used by the DTE to indicate
its intention to make a call or accept a call. -
The signal RING is used by the DCE to indicate
that there is an incoming call.
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Sequence of events occur during data transmission
over public phone line
time
Local
Remote (receiving side)
(transmission side)
Connection establishment phase
1. DTE asserts DTR
2. DCE dials the phone number
3. DCE detects the ring and asserts RING
4. DTE asserts DTR to accept the call
5. DCE sends out a carrier and asserts DSR
6. DCE asserts DSR and DCD and also sends
out a carrier for full duplex operation
7. DCE asserts DCD (full duplex operation)
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Sequence of events occur during data transmission
(continued)
time
Local
Remote (receiving side)
(transmission side)
Data transmission phase
1. DTE asserts RTS
2. DCE asserts CTS
3. DTE sends out data to DCE
4. DCE modulates data and sends it out
5. DCE demodulates data and forwards the
data to DTE
6. DTE receives data
Disconnection phase
1. DTE drops RTS
2. DCE drops CTS and drops the carrier
3. DCE deasserts DCD DSR
4. DTE deasserts DTR
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Data format for asynchronous data
communication - data is transmitted character by
character bit-serially - a character consists of
1. one start bit (0), 2. 7 to 8 data bits,
3. an optional parity bit, 4. one, or one and
a half, or two stop bits (1) 5. least
significant bit is transmitted first 6. most
significant bit is transmitted last
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Example 9.1 The letter A is to be transmitted.
What is the data output transmitted out from the
computer? The data format for transmission is 8
data bits, no parity, and one stop
bit. Solution The ASCII code of letter A is 41
or 01000001. This code will be followed by a
stop bit. The output from the DTE should be
Example 9.2 How long does it take to transmit one
character at the speed of 9600 baud?
Each character is transmitted using a format with
seven data bits, even parity, and two stop
bits. Solution - Each character consists 11
bits. - Each bit requires 104 ms ( 1 sec
9600). - One character requires 11 104 ms
1.145 ms to transmit.
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Data transmission errors - framing error a
character is not properly framed by a stop
bit - receiver overrun one or more characters
received but not read by the CPU - parity error
odd number of bits change value Null Modem
connection
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The 68HC11 SCI Subsystem - Signal pins TxD
(PD1) and RxD (PD0) - Data formats 1. one
start bit 2. 8 or 9 data bits 3. one stop
bit - Wake up feature 1. address mark wakeup
the character whose msb is a 1 is an address
mark 2. idle line wakeup the RxD pin is idle
(high) for at least one complete character
time Wakeup feature can reduce the data
communication overhead in a multidrop
environment. - Start bit detection 1. the SCI
uses a clock 16 times the bit rate to detect the
arrival of a start bit and data bit 2. the RxD
pin must be high for at least three sampling
clock cycles followed by a low voltage 3. the
majority of bits 3, 5, and 7 being a low is
considered as the arrival of a start bit
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- Receive process of a character 1. the
receiver detects the start bit 2. the receiver
shifts in 8 (or 9) data bits 3. the receiver
shifts in the stop bit 4. when a correct stop
bit is detected, the data bits will be loaded
into the receive data register 5. the receiver
sets the RDRF flag in the SCSR register and may
optionally generate an interrupt to the
CPU - SCI receive errors 1. framing error
(FE) 2. receiver overrun (OR) 3. noise error
(NE) - The transmitting process of a
character 1. CPU writes the character into the
transmit data register after the transmitter is
enabled 2. the transmitter adds the start bit
and a stop bit to the data character presented by
the CPU 3. the transmitter shifts out the bit
stream 4. the transmitter sets the TDRE status
flag of the SCSR register after a character is
shifted out and may optionally generate an
interrupt to the CPU
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SCI registers Serial Communication Data Register
(SCDR) Receive data register (RDR) and transmit
data register (TDR) are referred to as
SCDR. Serial Communication Status Register
(SCSR)
TDRE set to 1 when transmit data register is
empty TC set to 1 when transmission is complete
(the whole message have been sent out) RDRF set
to 1 when receive data register is full IDLE
set to 1 when idle line condition is
detected OR set to 1 when receiver is
overrun NF set to 1 when communication line is
noisy FE set to 1 when framing error occurs
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Serial Communication Control Register 1 (SCCR1)
R8 receive data bit 8 T8 transmit data bit
8 M data format bit (0 selects 8 data bits, 1
selects 9 data bits) WAKE wake up method select
(0 selects idle line, 1 selects address mark
wake up method)
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Serial Communication Control Register 2 (SCCR2)
TIE transmit interrupt enable TCIE transmit
complete interrupt enable RIE receive interrupt
enable (including receive data register full and
receiver overrun) ILIE idle line interrupt
enable TE transmit enable RE receive
enable RWU receiver wake up (puts the receiver
in sleep and enables wake up mechanism) SBK send
break
A break is defined as the transmission or
reception of a low for at least one
complete character frame time (from the viewpoint
of a DTE). An idle line is defined as a
continuous logic high on the RxD line for at
least a complete character frame time (from the
viewpoint of a DTE).
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Baud Register (BAUD)
TCLR clear baud rate counter (used in
factory testing only) RCKB SCI baud rate check
(used in factory testing only)
The baud rate is derived by dividing the E clock
signal by two factors specified in the BAUD
register.
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Example 9.3 Give a set of baud rate prescale and
baud rate select factors to set the baud rate to
9600 with a 2-MHz E clock. Solution - the
frequency of the clock that is used to determine
the bit value is 16 9600 153,000. - 13
153000 1996800 2 MHz. - set the prescale
factor to 13 (set SCP1 SCP0 to 11) - set the
baud rate select factor to 1 (set SCR2-SCR0 to
000) - write the value 30 to the BAUD register
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SCI Interfacing - the SCI uses 0 V and 5 V to
represent 0 and 1 - the RS232 signal Tx cannot be
driven by the SCI TxD signal without
translation - the RS232 signal Rx cannot drive
the SCI RxD signal without translation - voltage
level translation is required for the SCI signals
to drive and be driven by the RS232
signals - Companies such as MAXIM and Motorola
provide RS232 driver and receiver chips that
perform the required voltage translation - MAX232
from MAXIM is a RS232 driver chip that operates
off a single 5V power supply
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MAX232 signals
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Interfacing the 68HC11 SCI to the RS232 using
the MAX232 chip and implements the NULL modem
connection so that this connection can talk to a
PC directly.
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Example 9.4 Write a subroutine that initialize
the 68HC11 SCI subsystem to operate with the
following parameters - 9600 baud - 1 start
bit, 8 data bits, and 1 stop bit - no interrupt
for receive and transmit - enable receive and
transmit - idle line wakeup - do not send
break Solution
regbas equ 1000 baud equ 2B sccr1 equ
2C sccr2 equ 2D on_sci pshx psha ldx
regbas ldaa 30 staa baud,X ldaa 0 staa
sccr1,X ldaa 0C staa sccr2,X pula pulx rt
s
- to choose 9600 baud write 30 into BAUD - for
the remaining parameters, write 00 and 0C
into SCCR1 and SCCR2
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Example 9.5 Write a subroutine to send break to
the communication port controlled by the SCI
subsystem. The duration of the transmitted break
is approximately 200,000 E clock
cycles. Solution - A break can be sent by
setting the bit 0 of SCCR2 to 1. As long as this
bit is 1, the SCI will keep sending out break
characters. regbas EQU 1000 SCCR2 EQU
2D sendbrk PSHX LDX regbas BSET
SCCR2,X 01 set send break bit the following
3 instructions create a delay of about 100
ms LDY 28751 txwait DEY BNE
txwait BCLR SCCR2,X 01 clear the SBK
bit of SCCR2 PULX RTS
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C Function to Send Break for 100 ms void
send_break ( ) char i SCCR2 0x01 /
set the bit that triggers send break / TFLG1
0x40 / clear OC2 F flag / TOC2 TCNT
20000 / start an OC2 operation with 10 ms delay
/ for (i 0 i lt 10 i ) / wait for 100
ms / while (!(TFLG1 0x40)) TFLG1
0x40 TOC2 20000 SCCR2 0xFE /
stop send break /
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Example 9.6 Write a subroutine to output a
character from the SCI subsystem using the
polling method. The character to be output is in
accumulator A. Solution The subroutine will wait
until the TDRE bit is set to 1 and then send out
the character. regbas EQU 1000 SCSR EQU
23 offset of SCSR from regbas SCDR EQU
2F offset of SCDR from regbas TDRE EQU
80 mask to select the TDRE bit of
SCSR SCIputch PSHX LDX regbas BRCLR SCSR,X
TDRE wait until transmit data register is
empty ANDA 7F clear bit 7 STAA SCDR,X
send the character PULX RTS In C
language, define TDRE 0x80 void sci_putch (char
xch) while (!(SCSR TDRE)) SCDR xch
0x7F
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Example 9.7 Write a subroutine to input a
character from the SCI subsystem using the
polling method. The character will be returned
in accumulator A. Solution regbas EQU
1000 SCSR EQU 23 offset of SCSR from
regbas SCDR EQU 2F offset of SCDR from
regbas RDRF EQU 20 mask to select the RDRF
bit of SCSR SCIgetch PSHX LDX
regbas BRCLR SCSR,X RDRF wait until RDRF
bit is 1 LDAA SCDR,X read the
character PULX RTS In C language, define
RDRF 0x20 char sci_getch ( ) while (!(SCSR
RDRF)) / wait until the RDRF flag is set
/ return SCDR
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Serial Communication Interface Chips - A
general-purpose microprocessor needs an external
serial interface chip to communicate with other
computer. - The 68HC11 needs external serial
communication chips if it needs to talk to two
or more DTEs. - The Motorola 6850 ACIA, Intel
8251, Zilog Z8530, and Rockwell R6551 are among
the popular serial communication chips - Serial
communication chips are also called universal
asynchronous receiver and transmitter
(UART) - The Motorola 6850 is used in the EVB to
implement the terminal port
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The Motorola 6850 ACIA - was designed to work
with Motorola 8-bit microprocessors - can also
work with the 68000 family microprocessors and
also the 68HC11 - has two 8-bit data registers,
one each for receive and transmit - has a
programmable control register and a read-only
status register - the register select input in
conjunction with the R/W input to select one of
the four registers
4
TxCLK
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VCC
Table 8.4 MC6850 Register Selection
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Enable
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R/W
Reg Sel R/W Register 1
0 Tx Data Register 1 1 Rx
Data Register 0 0 Control
Register 0 1 Status Register
TxData
8
CS0
10
24
CS1
CTS
9
CS2
11
Reg Sel
23
DCD
6850
7
IRQ
5
RTS
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D0 D1 D2 D3 D4 D5 D6 D7
2
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RxData
20
19
18
1
17
VSS
16
3
15
RxCLK
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Control register
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Status Register
IRQ interrupt request flag PE parity
error OVRN overrun flag FE frame error
flag CTS clear to send flag that reflects the
current level of the CTS input from a
modem DCD data carrier detect flag. This bit
goes high when the DCD input from the modem goes
high (indicates no carrier condition) TDRE transm
it data register empty RDRF receive data
register full
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ACIA Transmit Operation Sequence - the CPU reads
the ACIA as a result of an interrupt or polling
sequence - the CPU writes a character into the
TDR if the TDRE bit of the status register is
1 - the ACIA transfers the character to the
transmit shift register to serialize the
character - the transmitter adds start bit, stop
bit(s) and optionally parity bit to the
serialized character before sending it to the
TxData pin ACIA Receive Operation
Sequence - the RxCLK clock which is either 1 or
16 or 64 times the bit rate is used to detect the
arrival of a start bit - for the divide-by-16 or
divide-by-64 counter divide factor, the start bit
is detected by 8 or 32 consecutive low samples
from the RxData pin - the ACIA receiver detects
the start bit - the ACIA shifts in the character
and discards the stop bit(s) - the ACIA records
parity, receiver overrun, and framing errors in
the status register ACIA Interrupts - one
transmit interrupt source transmit data register
empty - three receive interrupt sources receive
data register full, receiver overrun, and data
carrier detect goes high
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Interfacing ACIA to the 68HC11 - the 68HC11
should be configured to operate in expanded
mode - address space should be assigned to the
ACIA - an example of circuit connection is shown
in Figure 9.17
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Example 9.9 Implement the null modem connection
to the ACIA so that the 68HC11 can talk to a PC
via a straight-through RS232 cable and connector.
This implementation should allow the user to
select from the following baud rates 300, 600,
1200, 2400, 4800, and 9600. Solution - A
crystal oscillator will be needed to generate an
accurate and stable clock signal. A 2.4576 MHz
crystal oscillator is used in this example. - A
Schmidt-Trigger inverter circuit will be used to
convert the sinusoidal output of the oscillator
to a square wave. The 74HC14 is used. - A ripple
counter is needed to provide a choice of baud
rates. A 74HC4040 is used. By feeding the
output of the 74HC14 to the 74HC4040, the
frequencies of Q1-Q7 are 1.2288 MHz, 0.6144 MHz,
0.3072 MHz, 0.1536 MHz, 0.0768 MHz, 0.0384 MHz,
and 0.0192 MHz. - Choosing 64 as the divide
factor for the receive clock, baud rates of 9600,
4800, 2400, 1200, 600, and 300 are obtained.
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- Use a MAX232 to perform voltage level
translation and implement the Null
modem connection as shown in Figure 9.20.
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Example 9.10 Write an instruction sequence to
configure the ACIA in Figure 9.20 to operate with
the following parameters - disable receive and
transmit interrupts - counter divide factor is
64 - data format is 8 data bits, 1 stop bit, and
no parity Solution - To disable receive
interrupts, clear the bit 7 of the ACIA control
register. - To disable transmit interrupt, set
bits 6 and 5 of the ACIA control register to 00
or 11. - For the chosen data format, set bits 4-2
of the control register to 101. - Set bits 1-0 of
the control register to 10 to select the
specified divide factor. - The address space
assigned to the ACIA is 9800-9FFF. acia_ini EQU
16 LDAA acia_ini STAA 9800
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A Terminal I/O Package for ACIA ONACIA initialize
s the ACIA control register GETCH returns a
character in accumulator A from the ACIA receive
data register PUTCH writes the contents of
accumulator A into the ACIA transmit data
register GETSTR inputs a string that is
terminated by a carriage return (CR). The string
is to be stored in the buffer pointed to by
Y. PUTSTR outputs a Null-terminated string
pointed to by Y NEWLINE outputs a CR/LF character
pair to the terminal CHPRSNT clears the Z bit in
CCR to 0 if a character is present in the ACIA
receive data register otherwise sets the Z flag
to 1. PUTHEX prints in 2 hex digits the 8-bit
contents of A ECHOFF turns off keyboard input
echoing (to the screen) ECHO turns on keyboard
input echoing (to the screen) LFON expands a CR
into CR/LF pair and expands a LF into LF/CR
pair LFOFF turns off newline expansion
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Constant definitions for the ACIA I/O
package ACIA equ 9800 base address of the
ACIA CR equ 0D ASCII code of carriage
return LF equ 0A ASCII code of line
feed TDRE equ 02 mask to select the transmit
data register empty flag RDRF equ 01 mask to
select the receive data register full
flag control equ 0 offset of the ACIA
control register from its base address status equ
0 offset of the ACIA status register from
its base address xmit equ 01 offset of the
ACIA transmit data register from its base
address rcv equ 01 offset of the ACIA
receive data register from its base
address masterst equ 03 value to reset ACIA
control register ctl_ini equ 16 value to
initialize the ACIA control register ONACIA pshx
psha ldx ACIA ldaa masterst reset
the ACIA staa control,X ldaa
ctl_ini set up ACIA parameters staa
control,X pula pulx rts
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In C language, we need to add the following
declaration to the hc11.h file so that we can
use symbols to access ACIA registers define
ACIA_CTRL (unsigned char volatile
)(0x9800) define ACIA_STAT (unsigned char
volatile )(0x9800) define ACIA_XMIT (unsigned
char volatile )(0x9801) define ACIA_RCV
(unsigned char volatile )(0x9801) ACIA
initialization in C language void on_acia (
) ACIA_CTRL 0x03 / master reset ACIA
/ ACIA_CTRL 0x16 / configure ACIA
parameters /
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Flowchart of Getch
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GETCH PSHX PSHB LDX ACIA The following
instruction checks framing, parity, and overrun
errors retry BRCLR status,X 70 noerr JSR
ONACIA reset ACIA BRA retry The next
instruction checks if receive data register is
full noerr BRCLR status,X RDRF
retry getit LDAA rcv,X read the
character ANDA 7F mask out bit 7 LDAB
echo is echo flag on? BEQ quit
JSR PUTCH echo the character quit PULB PULX
RTS
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C Language Version of Getch char getchar (
) char xch while (ACIA_STAT 0x70)
on_acia ( ) while (!(ACIA_STAT
0x01)) / wait until receive data register is
full / xch ACIA_RCV 0x7F / mask out
parity bit / if (ECHO_ON) putchar (xch) /
echo the character to the screen / return xch
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Flowchart of PUTCH routine
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PUTCH BSR outch TST autolf check auto line
feed flag BEQ quit prepare to return if
not CMPA CR does A contains a CR? BNE
chklf go and check LF LDAA LF also output
a LF BSR outch BRA quit chklf CMPA
LF does A contains a LF? BNE quit
prepare to return if not LDAA CR also
output a CR BSR outch quit RTS outch LDX
ACIA BRCLR status,X TDRE wait until xmit
empty STAA xmit,X output the character RTS
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C Function that Outputs A Character char
auto_lf void outchar (xch) define CR
0x0D define LF 0x0A while
(!(ACIA_STAT 0x02)) void outchar (char xch)
ACIA_XMIT xch void putchar (char
xch) outchar (xch) if (auto_lf)
switch (xch) case CR outchar
(LF) break case LF outchar
(CR) break default break
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GETSTR PSHA gsloop JSR GETCH get a
character CMPA CR is it a carriage
return? BEQ gfinis if yes, then it is the
end of the string STAA 0,Y save the
character INY move the pointer BRA
gsloop gfinis LDAA 00 add a Null to the
end of the string STAA 0,Y PULA RTS PUT
STR PSHA psloop LDAA 0,Y BEQ pfinis is this
the end of the string? JSR PUTCH if not,
output the character INY move to the next
character BRA psloop pfinis PULA RTS
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GETSTR Function in C void getstr (char
ptr) char xch while ((xch getchar ( ))
! \n) ptr xch ptr \0 PUTSTR
Function in C void putstr (char ptr) while
(ptr) putchar (ptr) ptr
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NEWLINE PSHA LDAA 01 set the auto
linefeed expansion flag STAA autolf LDAA
CR output a carriage return JSR PUTCH
output a CR which will be expanded into CR/LF
pair PULA CLR autolf clear the auto line
feed expansion flag RTS In C language, void
newline ( ) auto_lf 1 / set auto-linefeed
flag / putchar (CR) auto_lf 0
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CHPRSNT PSHA PAHX LDX ACIA LDAA status,X
BITA RDRF test the RDRF flag to update the Z
flag of CCR PULX PULA RTS In C
language, int chprsnt ( ) if (ACIA_STAT
0x01) return 1 else return 0
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PUTHEX PSHX PSHB PSHA TAB make a copy of A
in B LSRB shift the upper hex digit LSRB
to the lower half of B LSRB LSRB LDX
hexdig place the address of the hex digit
table in X ABX point X to the ASCII code of
the upper hex digit in A LDAA 0,X get the
ASCII code JSR PUTCH output the upper hex
digit PULB put A in B again PSHB restore
the stack ANDB 0F mask out the upper
digit LDX hexdig place the address of the hex
table digit in X ABX point X to the ASCII
code of the lower hex digit in A LDAA 0,X get
the ASCII code of the lower hex
digit JSR PUTCH output the hex
digit PULA PULB PULX RTS hexdig FCC 012345678
9ABCDEF hex digits ASCII code table
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PUTHEX Function in C Language char hex_tab 16
0, 1, 2, 3, 4, 5, 6, 7, 8,
9, A, B, C, D, E, F void puthex
(xch) char xx xx xch 0xF0 / mask out
the lower 4 bits / xx xx gtgt 4 putchar
(hex_tabxx) xx xch 0x0F / mask out the
upper 4 bits / putchar (hex_tabxx)
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ECHOFF CLR echo turn off input
echoing RTS ECHON LDAA 1 STAA echo turn on
input echoing RTS LFON LDAA 1 STAA autolf
turn on auto line feed expansion RTS LFOFF CLR a
utolf turn off auto line feed
expansion RTS echo RMB 1 input echo
flag autolf RMB 1 line feed expansion flag END