Microprocessors course

1
In The Name Of God
Microcontroller 8051

• Section 1
• Microprocessors course
• Dr. S.O.Fatemi
• By Mahdi Hassanpour

2
Contents

• Introduction
• Block Diagram and Pin Description of the 8051
• Registers
• Some Simple Instructions
• Structure of Assembly language and Running an
  8051 program
• Memory mapping in 8051
• 8051 Flag bits and the PSW register
• Addressing Modes
• 16-bit, BCD and Signed Arithmetic in 8051
• Stack in the 8051
• LOOP and JUMP Instructions
• CALL Instructions
• I/O Port Programming

3
Introduction
General-purpose microprocessor

• CPU for Computers
• No RAM, ROM, I/O on CPU chip itself
• ExampleIntels x86, Motorolas 680x0

Many chips on mothers board
Data Bus
CPU General-Purpose Micro-processor
Serial COM Port
I/O Port
RAM
ROM
Timer
Address Bus
General-Purpose Microprocessor System
4
Microcontroller

• A smaller computer
• On-chip RAM, ROM, I/O ports...
• ExampleMotorolas 6811, Intels 8051, Zilogs Z8
  and PIC 16X

RAM
ROM
CPU
A single chip
Serial COM Port
I/O Port
Timer
Microcontroller
5
Microprocessor vs. Microcontroller

• Microprocessor
• CPU is stand-alone, RAM, ROM, I/O, timer are
  separate
• designer can decide on the amount of ROM, RAM
  and I/O ports.
• expansive
• versatility
• general-purpose

• Microcontroller
• CPU, RAM, ROM, I/O and timer are all on a single
  chip
• fix amount of on-chip ROM, RAM, I/O ports
• for applications in which cost, power and space
  are critical
• single-purpose

6
Embedded System

• Embedded system means the processor is embedded
  into that application.
• An embedded product uses a microprocessor or
  microcontroller to do one task only.
• In an embedded system, there is only one
  application software that is typically burned
  into ROM.
• Exampleprinter, keyboard, video game player

7
Three criteria in Choosing a Microcontroller

• meeting the computing needs of the task
  efficiently and cost effectively
• speed, the amount of ROM and RAM, the number of
  I/O ports and timers, size, packaging, power
  consumption
• easy to upgrade
• cost per unit
• availability of software development tools
• assemblers, debuggers, C compilers, emulator,
  simulator, technical support
• wide availability and reliable sources of the
  microcontrollers.

8
Block Diagram
External interrupts
On-chip ROM for program code
Timer/Counter
Interrupt Control
Timer 1
On-chip RAM
Counter Inputs
Timer 0
CPU
Serial Port
Bus Control
4 I/O Ports
OSC
TxD RxD
P0 P1 P2 P3
Address/Data
9
Comparison of the 8051 Family Members

• Feature
  8051 8052 8031
• ROM (program space in bytes) 4K 8K
  0K
• RAM (bytes) 128
  256 128
• Timers
  2 3 2
• I/O pins
  32 32 32
• Serial port
  1 1 1
• Interrupt sources 6
  8 6

10
(No Transcript)
11
Pin Description of the 8051
PDIP/Cerdip
?
12
Pins of 8051(1/4)

• Vcc(pin 40)
• Vcc provides supply voltage to the chip.
• The voltage source is 5V.
• GND(pin 20)ground
• XTAL1 and XTAL2(pins 19,18)
• These 2 pins provide external clock.
• Way 1using a quartz crystal oscillator ?
• Way 2using a TTL oscillator ?
• Example 4-1 shows the relationship between XTAL
  and the machine cycle. ?

13
Pins of 8051(2/4)

• RST(pin 9)reset
• It is an input pin and is active high(normally
  low).
• The high pulse must be high at least 2 machine
  cycles.
• It is a power-on reset.
• Upon applying a high pulse to RST, the
  microcontroller will reset and all values in
  registers will be lost.
• Reset values of some 8051 registers ?
• Way 1Power-on reset circuit ?
• Way 2Power-on reset with debounce ?

14
Pins of 8051(3/4)

• /EA(pin 31)external access
• There is no on-chip ROM in 8031 and 8032 .
• The /EA pin is connected to GND to indicate the
  code is stored externally.
• /PSEN ALE are used for external ROM.
• For 8051, /EA pin is connected to Vcc.
• / means active low.
• /PSEN(pin 29)program store enable
• This is an output pin and is connected to the OE
  pin of the ROM.
• See Chapter 14.

15
Pins of 8051(4/4)

• ALE(pin 30)address latch enable
• It is an output pin and is active high.
• 8051 port 0 provides both address and data.
• The ALE pin is used for de-multiplexing the
  address and data by connecting to the G pin of
  the 74LS373 latch.
• I/O port pins
• The four ports P0, P1, P2, and P3.
• Each port uses 8 pins.
• All I/O pins are bi-directional.

16
Figure 4-2 (a). XTAL Connection to 8051

• Using a quartz crystal oscillator
• We can observe the frequency on the XTAL2 pin.

?
17
Figure 4-2 (b). XTAL Connection to an External
Clock Source

• Using a TTL oscillator
• XTAL2 is unconnected.

?
18
Example
Find the machine cycle for (a) XTAL 11.0592 MHz
(b) XTAL 16 MHz. Solution (a) 11.0592 MHz /
12 921.6 kHz machine cycle 1 / 921.6
kHz 1.085 ?s (b) 16 MHz / 12 1.333 MHz
machine cycle 1 / 1.333 MHz 0.75 ?s
?
19
RESET Value of Some 8051 Registers
Reset Value
Register
0000
PC
0000
ACC
0000
B
0000
PSW
0007
SP
0000
DPTR
RAM are all zero.
?
20
Figure 4-3 (a). Power-On RESET Circuit
Vcc

10 uF
31
EA/VPP
X1
30 pF
19
11.0592 MHz
8.2 K
X2
18
30 pF
RST
9
?
21
Figure 4-3 (b). Power-On RESET with Debounce
Vcc
31
EA/VPP
X1
10 uF
30 pF
X2
RST
9
8.2 K
?
22
Pins of I/O Port

• The 8051 has four I/O ports
• Port 0 (pins 32-39)P0(P0.0P0.7)
• Port 1(pins 1-8) P1(P1.0P1.7)
• Port 2(pins 21-28)P2(P2.0P2.7)
• Port 3(pins 10-17)P3(P3.0P3.7)
• Each port has 8 pins.
• Named P0.X (X0,1,...,7), P1.X, P2.X, P3.X
• ExP0.0 is the bit 0(LSB)of P0
• ExP0.7 is the bit 7(MSB)of P0
• These 8 bits form a byte.
• Each port can be used as input or output
  (bi-direction).

?
23
Registers
24
Some Simple Instructions

• MOV dest,source dest source
• MOV A,72H A72H
• MOV A, r Ar OR 72H
• MOV R4,62H R462H
• MOV B,0F9H Bthe content of F9th byte of RAM
• MOV DPTR,7634H
• MOV DPL,34H
• MOV DPH,76H
• MOV P1,A mov A to port 1
• Note 1
• MOV A,72H ? MOV A,72H
• After instruction MOV A,72H the content of
  72th byte of RAM will replace in Accumulator.
• 8086 8051
• MOV AL,72H MOV A,72H

25

• ADD A, Source AASOURCE
• ADD A,6 AA6
• ADD A,R6 AAR6
• ADD A,6 AA6 or AAR6
• ADD A,0F3H AA0F3H

26

• SETB bit bit1
• CLR bit bit0
• SETB C CY1
• SETB P0.0 bit 0 from port 0 1
• SETB P3.7 bit 7 from port 3 1
• SETB ACC.2 bit 2 from ACCUMULATOR 1
• SETB 05 set high D5 of RAM loc. 20h
• Note
• CLR instruction is as same as SETB
• i.e
• CLR C CY0
• But following instruction is only for CLR
• CLR A A0

• Bit Addressable
• Page 359,360

27

• SUBB A,source AA-source-CY
• SETB C CY1
• SUBB A,R5 AA-R5-1
• ADC A,source AAsourceCY
• SETB C CY1
• ADC A,R5 AAR51

28

• DEC byte bytebyte-1
• INC byte bytebyte1
• INC R7
• DEC A
• DEC 40H 4040-1
• CPL A 1s complement
• Example
• MOV A,55H A01010101 B
• L01 CPL A
• MOV P1,A
• ACALL DELAY
• SJMP L01
• NOP RET RETI
• All are like 8086 instructions.

? CALL
29

• ANL - ORL - XRL
• EXAMPLE
• MOV R5,89H
• ANL R5,08H
• RR RL RRC RLC A
• EXAMPLE
• RR A

30
Structure of Assembly language and Running an
8051 program

• ORG 0H
• MOV R5,25H
• MOV R7,34H
• MOV A,0
• ADD A,R5
• ADD A,12H
• HERE SJMP HERE
• END

31
Memory mapping in 8051

• ROM memory map in 8051 family

4k
8k
32k
DS5000-32
from Atmel Corporation
from Dallas Semiconductor
32

• RAM memory space allocation in the 8051

33
8051 Flag bits and the PSW register

• PSW Register

34
Instructions that Affect Flag Bits
Note X can be 0 or 1
35
Example MOV A,88H ADD A,93H 88
10001000 93 10010011 ----
-------------- 11B 00011011 CY1 AC0 P0
Example MOV A,9CH ADD A,64H 9C
10011100 64 01100100 ----
-------------- 100 00000000 CY1 AC1 P0

• Example
• MOV A,38H
• ADD A,2FH
• 38 00111000
• 2F 00101111
• ---- --------------
• 67 01100111
• CY0 AC1 P1

36
Addressing Modes

• Immediate
• Register
• Direct
• Register Indirect
• Indexed

37
Immediate Addressing Mode

• MOV A,65H
• MOV A,A
• MOV R6,65H
• MOV DPTR,2343H
• MOV P1,65H
• Example
• Num EQU 30
• MOV R0,Num
• MOV DPTR,data1
• ORG 100H
• data1 db IRAN

38
Register Addressing Mode

• MOV Rn, A n0,..,7
• ADD A, Rn
• MOV DPL, R6
• MOV DPTR, A
• MOV Rm, Rn

39
Direct Addressing Mode

• Although the entire of 128 bytes of RAM can be
  accessed using direct addressing mode, it is most
  often used to access RAM loc. 30 7FH.
• MOV R0, 40H
• MOV 56H, A
• MOV A, 4 MOV A, R4
• MOV 6, 2 copy R2 to R6
• MOV R6,R2 is invalid !
• SFR register and their address
• MOV 0E0H, 66H MOV A,66H
• MOV 0F0H, R2 MOV B, R2
• MOV 80H,A MOV P1,A

• Bit Addressable
• Page 359,360

40
Register Indirect Addressing Mode

• In this mode, register is used as a pointer to
  the data.
• MOV A,_at_Ri move content of RAM loc.Where
  address is held by Ri into A
• ( i0 or 1 )
• MOV _at_R1,B
• In other word, the content of register R0 or R1
  is sources or target in MOV, ADD and SUBB
  insructions.
• Example
• Write a program to copy a block of 10 bytes from
  RAM location sterting at 37h to RAM location
  starting at 59h.
• Solution
• MOV R0,37h source pointer
• MOV R1,59h dest pointer
• MOV R2,10 counter
• L1 MOV A,_at_R0
• MOV _at_R1,A
• INC R0
• INC R1
• DJNZ R2,L1

• jump

41
Indexed Addressing Mode And On-Chip ROM Access

• This mode is widely used in accessing data
  elements of look-up table entries located in the
  program (code) space ROM at the 8051
• MOVC A,_at_ADPTR
• A content of address A DPTR from ROM
• Note
• Because the data elements are stored in the
  program (code ) space ROM of the 8051, it uses
  the instruction MOVC instead of MOV. The C
  means code.

42

• Example
• Assuming that ROM space starting at 250h
  contains Hello., write a program to transfer
  the bytes into RAM locations starting at 40h.
• Solution
• ORG 0
• MOV DPTR,MYDATA
• MOV R0,40H
• L1 CLR A
• MOVC A,_at_ADPTR
• JZ L2
• MOV _at_R0,A
• INC DPTR
• INC R0
• SJMP L1
• L2 SJMP L2
• -------------------------------------
• ORG 250H
• MYDATA DB Hello,0
• END

43

• Example
• Write a program to get the x value from P1 and
  send x2 to P2, continuously .
• Solution
• ORG 0
• MOV DPTR, TAB1
• MOV A,0FFH
• MOV P1,A
• L01
• MOV A,P1
• MOVC A,_at_ADPTR
• MOV P2,A
• SJMP L01
• -------------------------------------------------
  ---
• ORG 300H
• TAB1 DB 0,1,4,9,16,25,36,49,64,81
• END

44
16-bit, BCD and Signed Arithmetic in 8051

• Exercise
• Write a program to add n 16-bit number. Get n
  from port 1. And sent Sum to LCD
• a) in hex
• b) in decimal
• Write a program to subtract P1 from P0 and send
  result to LCD
• (Assume that ACAL DISP display A to LCD )

45
MUL DIV

• MUL AB BA AB
• MOV A,25H
• MOV B,65H
• MUL AB 25H65H0E99
• B0EH, A99H
• MUL AB A A/B, B A mod B
• MOV A,25
• MOV B,10
• MUL AB A2, B5

46
Stack in the 8051

• The register used to access the stack is called
  SP (stack pointer) register.
• The stack pointer in the 8051 is only 8 bits
  wide, which means that it can take value 00 to
  FFH. When 8051 powered up, the SP register
  contains value 07.

47
Example MOV R6,25H MOV R1,12H MOV R4,0F3H
PUSH 6 PUSH 1 PUSH 4
48
LOOP and JUMP Instructions

• DJNZ
• Write a program to clear ACC, then
• add 3 to the accumulator ten time
• Solution
• MOV A,0
• MOV R2,10
• AGAIN ADD A,03
• DJNZ R2,AGAING repeat until R20 (10 times)
• MOV R5,A

49

• Other conditional jumps

JZ Jump if A0
JNZ Jump if A/0
DJNZ Decrement and jump if A/0
CJNE A,byte Jump if A/byte
CJNE reg,data Jump if byte/data
JC Jump if CY1
JNC Jump if CY0
JB Jump if bit1
JNB Jump if bit0
JBC Jump if bit1 and clear bit
50

• SJMP and LJMP
• LJMP(long jump)
• LJMP is an unconditional jump. It is a 3-byte
  instruction in which the first byte is the
  opcode, and the second and third bytes represent
  the 16-bit address of the target location. The
  20byte target address allows a jump to any memory
  location from 0000 to FFFFH.
• SJMP(short jump)
• In this 2-byte instruction. The first byte is
  the opcode and the second byte is the relative
  address of the target location. The relative
  address range of 00-FFH is divided into forward
  and backward jumps, that is , within -128 to 127
  bytes of memory relative to the address of the
  current PC.

51
CJNE , JNC

• Exercise
• Write a program that compare R0,R1.
• If R0gtR1 then send 1 to port 2,
• else if R0ltR1 then send 0FFh to port 2,
• else send 0 to port 2.

52
CALL Instructions

• Another control transfer instruction is the CALL
  instruction, which is used to call a subroutine.
• LCALL(long call)
• In this 3-byte instruction, the first byte is
  the opcode an the second and third bytes are used
  for the address of target subroutine. Therefore,
  LCALL can be used to call subroutines located
  anywhere within the 64K byte address space of the
  8051.

53

• ACALL (absolute call)
• ACALL is 2-byte instruction in contrast to
  LCALL, which is 13 bytes. Since ACALL is a 2-byte
  instruction, the target address of the subroutine
  must be within 2K bytes address because only 11
  bits of the 2 bytes are used for the address.
  There is no difference between ACALL and LCALL in
  terms of saving the program counter on the stack
  or the function of the RET instruction. The only
  difference is that the target address for LCALL
  can be anywhere within the 64K byte address space
  of the 8051 while the target address of ACALL
  must be within a 2K-byte range.

54
I/O Port Programming
Port 1(pins 1-8)
?

• Port 1 is denoted by P1.
• P1.0 P1.7
• We use P1 as examples to show the operations on
  ports.
• P1 as an output port (i.e., write CPU data to the
  external pin)
• P1 as an input port (i.e., read pin data into CPU
  bus)

55
A Pin of Port 1
?P0.x
8051 IC
56
Hardware Structure of I/O Pin

• Each pin of I/O ports
• Internal CPU buscommunicate with CPU
• A D latch store the value of this pin
• D latch is controlled by Write to latch
• Write to latch1write data into the D latch
• 2 Tri-state buffer?
• TB1 controlled by Read pin
• Read pin1really read the data present at the
  pin
• TB2 controlled by Read latch
• Read latch1read value from internal latch
• A transistor M1 gate
• Gate0 open
• Gate1 close

57
Tri-state Buffer
Output
Input
Tri-state control (active high)
H
Low
L
H
L
Highimpedance (open-circuit)
H
H
?
58
Writing 1 to Output Pin P1.X
TB2
2. output pin is Vcc
1. write a 1 to the pin
1
output 1
0
TB1
8051 IC
59
Writing 0 to Output Pin P1.X
TB2
2. output pin is ground
1. write a 0 to the pin
0
output 0
1
TB1
8051 IC
60
Port 1 as Output(Write to a Port)

• Send data to Port 1
• MOV A,55H
• BACK MOV P1,A
• ACALL DELAY
• CPL A
• SJMP BACK
• Let P1 toggle.
• You can write to P1 directly.

61
Reading Input v.s. Port Latch

• When reading ports, there are two possibilities
• Read the status of the input pin. (from external
  pin value)
• MOV A, PX
• JNB P2.1, TARGET jump if P2.1 is not set
• JB P2.1, TARGET jump if P2.1 is set
• Figures C-11, C-12
• Read the internal latch of the output port.
• ANL P1, A P1 ? P1 AND A
• ORL P1, A P1 ? P1 OR A
• INC P1 increase P1
• Figure C-17
• Table C-6 Read-Modify-Write Instruction (or Table
  8-5)
• See Section 8.3

62
Reading High at Input Pin
2. MOV A,P1 external pinHigh
TB2

1. write a 1 to the pin MOV P1,0FFH

1
1
0
TB1
3. Read pin1 Read latch0 Write to latch1
8051 IC
63
Reading Low at Input Pin
2. MOV A,P1 external pinLow
TB2

• write a 1 to the pin
• MOV P1,0FFH

1
0
0
TB1
3. Read pin1 Read latch0 Write to latch1
8051 IC
64
Port 1 as Input(Read from Port)

• In order to make P1 an input, the port must be
  programmed by writing 1 to all the bit.
• MOV A,0FFH A11111111B
• MOV P1,A make P1 an input port
• BACK MOV A,P1 get data from P0
• MOV P2,A send data to P2
• SJMP BACK
• To be an input port, P0, P1, P2 and P3 have
  similar methods.

65
Instructions For Reading an Input Port

• Following are instructions for reading external
  pins of ports

Mnemonics Examples Description
MOV A,PX MOV A,P2 Bring into A the data at P2 pins
JNB PX.Y,.. JNB P2.1,TARGET Jump if pin P2.1 is low
JB PX.Y,.. JB P1.3,TARGET Jump if pin P1.3 is high
MOV C,PX.Y MOV C,P2.4 Copy status of pin P2.4 to CY
66
Reading Latch

• Exclusive-or the Port 1
• MOV P1,55H P101010101
• ORL P1,0F0H P111110101
• 1. The read latch activates TB2 and bring the
  data from the Q latch into CPU.
• Read P1.00
• 2. CPU performs an operation.
• This data is ORed with bit 1 of register A. Get
  1.
• 3. The latch is modified.
• D latch of P1.0 has value 1.
• 4. The result is written to the external pin.
• External pin (pin 1 P1.0) has value 1.

67
Reading the Latch
1. Read pin0 Read latch1 Write to latch0
(Assume P1.X0 initially)
TB2
2. CPU compute P1.X OR 1
4. P1.X1
0
0
1
1
0
3. write result to latch Read pin0
Read latch0 Write to latch1
TB1
8051 IC
68
Read-modify-write Feature

• Read-modify-write Instructions
• Table C-6
• This features combines 3 actions in a single
  instruction
• 1. CPU reads the latch of the port
• 2. CPU perform the operation
• 3. Modifying the latch
• 4. Writing to the pin
• Note that 8 pins of P1 work independently.

69
Port 1 as Input(Read from latch)

• Exclusive-or the Port 1
• MOV P1,55H P101010101
• AGAIN XOR P1,0FFH complement
• ACALL DELAY
• SJMP AGAIN
• Note that the XOR of 55H and FFH gives AAH.
• XOR of AAH and FFH gives 55H.
• The instruction read the data in the latch (not
  from the pin).
• The instruction result will put into the latch
  and the pin.

70
Read-Modify-Write Instructions
Example
Mnemonics
71
You are able to answer this Questions

• How to write the data to a pin?
• How to read the data from the pin?
• Read the value present at the external pin.
• Why we need to set the pin first?
• Read the value come from the latch(not from the
  external pin).
• Why the instruction is called read-modify write?

72
Other Pins

• P1, P2, and P3 have internal pull-up resisters.
• P1, P2, and P3 are not open drain.
• P0 has no internal pull-up resistors and does not
  connects to Vcc inside the 8051.
• P0 is open drain.
• Compare the figures of P1.X and P0.X. ?
• However, for a programmer, it is the same to
  program P0, P1, P2 and P3.
• All the ports upon RESET are configured as output.

73
A Pin of Port 0
?P1.x
8051 IC
74
Port 0(pins 32-39)

• P0 is an open drain.
• Open drain is a term used for MOS chips in the
  same way that open collector is used for TTL
  chips. ?
• When P0 is used for simple data I/O we must
  connect it to external pull-up resistors.
• Each pin of P0 must be connected externally to a
  10K ohm pull-up resistor.
• With external pull-up resistors connected upon
  reset, port 0 is configured as an output port.

75
Port 0 with Pull-Up Resistors
76
Dual Role of Port 0

• When connecting an 8051/8031 to an external
  memory, the 8051 uses ports to send addresses and
  read instructions.
• 8031 is capable of accessing 64K bytes of
  external memory.
• 16-bit addressP0 provides both address A0-A7, P2
  provides address A8-A15.
• Also, P0 provides data lines D0-D7.
• When P0 is used for address/data multiplexing, it
  is connected to the 74LS373 to latch the address.
• There is no need for external pull-up resistors
  as shown in Chapter 14.

77
74LS373
78
Reading ROM (1/2)
2. 74373 latches the address and send to ROM
1. Send address to ROM
Address
79
Reading ROM (2/2)
2. 74373 latches the address and send to ROM
Address
3. ROM send the instruction back
80
ALE Pin

• The ALE pin is used for de-multiplexing the
  address and data by connecting to the G pin of
  the 74LS373 latch.
• When ALE0, P0 provides data D0-D7.
• When ALE1, P0 provides address A0-A7.
• The reason is to allow P0 to multiplex address
  and data.

81
Port 2(pins 21-28)

• Port 2 does not need any pull-up resistors since
  it already has pull-up resistors internally.
• In an 8031-based system, P2 are used to provide
  address A8-A15.

82
Port 3(pins 10-17)

• Port 3 does not need any pull-up resistors since
  it already has pull-up resistors internally.
• Although port 3 is configured as an output port
  upon reset, this is not the way it is most
  commonly used.
• Port 3 has the additional function of providing
  signals.
• Serial communications signalRxD, TxD(Chapter 10)
• External interrupt/INT0, /INT1(Chapter 11)
• Timer/counterT0, T1(Chapter 9)
• External memory accesses in 8031-based
  system/WR, /RD(Chapter 14)

83
Port 3 Alternate Functions
?