Computer Organization Lecture 8

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Computer OrganizationLecture 8

• Detailed MIPS datapath
• Timing overview

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Project 2 overview

• Sixteen-bit ALU
• Use four LS181 plus some other logic
• Arithmetic , -
• Logical
• and, or
• shift left, shift right

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Project 2 hints

• Use four LS181s ALU
• Design shifter circuits
• Use muxes to select between ALU and shifters
• Design combinational logic to control muxes
  consider a ROM

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Project 2 questions?
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MIPS datapath overview

• Instruction read from memory
• Registers selected for operation
• ALU performs function
• Result written to register

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Shift register review
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Shift register operation

• Clock Reset connected/bused to each flip-flop
• With Sin 1, data moves left-to-right on each
  clock edge (1000, 1100, 1110, 1111)
• We could modify the design
• 32-bit shift register
• Add combinational logic between flip-flops

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MIPS datapath

• Information moves left-to-right

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Key elements of datapath

• Shared memory instructions and data
• Single ALU
• PC increment by 4
• Functions , -, and, or, etc.
• Determines effective branch/jump addresses
• Temporary registers hold data between clock
  edges (like shift register does)

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New temporary registers

• Instruction (IR) holds current instruction
• Memory data (MDR) holds data read from memory
• A, B holds data from register file
• ALUout holds ALU output (Project 2)

Note All of these are D-type flip-flops
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MIPS datapath
Clock 5
Clock Driver

• Data travels left-to-right on each clock edge

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Example timing
1
2
3
4
5
Instructions vary from 3 5 clocks
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Complete the table?
Instruction Total Clocks Clock Clock Clock Clock Clock
Instruction Total Clocks 1 2 3 4 5
add 1, 2, 3 4 x x x x
beq 1, 2, label 4 x x x
lw 1, offset (2) 5 x x x x x
sub 1, 2, 3 4 x x x x
sw 1, offset (2) 4 x x x x
j label 3 x x x
1 Instruction Fetch 2 Decode Register
Read 3 Execution
4 Memory Access 5 Register Write
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Datapath organization detail
4
2
1
3
5
Five muxes select between various sources
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Muxes added

1. Address for memory PC or ALU
2. Write register rs or rt
3. Write data memory, ALU
4. ALU first operand PC, Register 1
5. ALU second operand Register 2, 0x4, sign
   extended, sign extended shifted 2

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Timing parameters
tsu
tprop

• D flip-flop has setup and propagation delays

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Synchronous logic
Register
Register
Edge-triggered logic

• Clock period gt Tprop Tcomb Tset

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Find the Fmax?
Assume mem, reg, ALU dominant terms
Mem 20 ns Reg 15 ns ALU 55 ns
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Now add controller signals
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What do these signals do?
Signal Function?
IorD Controls address of memory PC, ALU
MemRead Puts memory in read mode
MemWrite Puts memory in write mode
IRWrite Write data to instruction register
RegDst Rs or rt for register write data
RegWrite Puts registers in write mode

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What do these signals do?
Signal Function?
ALUSrcA Data for A input of ALU
ALUOp Function code for ALU
ALUSrcB Data for B input of ALU
MemtoReg Data for the register write memory, ALU

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Branch and jump additions

• Next PC value, three possible sources
• PC4 ALU output
• Branch target ALUout register
• Jump address concatenation of PC31-28, IR25-0
  shifted left 2, two lsb of zero
• PC write control
• PCWrite unconditional (increments, jump)
• PCWriteCond conditional write for branch

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Complete datapath
new
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Datapath and controller
Controller Input
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(No Transcript)
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Complete the table?
Instruction Total Clocks Clock Clock Clock Clock Clock
Instruction Total Clocks 1 2 3 4 5
add 1, 2, 3 4 x x x x
beq 1, 2, label 3 x x x
lw 1, offset (2) 5 x x x x x
sub 1, 2, 3 3 x x x x
sw 1, offset (2) 4 x x x x
j label 3 x x x
1 Instruction Fetch 2 Decode Register
Read 3 Execution
4 Memory Access 5 Register Write
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Find the Fmax?
Assume mem, reg, ALU dominant terms
15 ns
55 ns
20 ns
Mem 20 ns Reg 15 ns ALU 55 ns Fmax
1/55ns 18.1 MHz
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What do these signals do?
Signal Function?
IorD Controls address of memory PC, ALU
MemRead Puts memory in read mode
MemWrite Data written to memory
IRWrite Data written to IR
RegDst Selects rs or rt for register write
RegWrite Data written to register file

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What do these signals do?
Signal Function?
ALUSrcA Determines ALU first operand
ALUOp Defines ALU function (, -, etc.)
ALUSrcB Determines ALU second operand
MemtoReg Memory or ALU is data for register write