Processor (I)

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Processor (I)
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The Processor Datapath Control

• We're ready to look at an implementation of the
  MIPS
• Simplified ISA to contain only
• Memory-reference instructions lw, sw
• Arithmetic-logical instructions add, sub, and,
  or, slt
• Control flow instructions beq, j
• Generic implementation
• Use the program counter (PC) to supply
  instruction address
• Get the instruction from memory
• Read registers
• Use the instruction to decide exactly what to do
• All instructions use the ALU after reading the
  registers
• Memory-reference? arithmetic? control flow?

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More Implementation Details

• Abstract / Simplified View
• Five steps to execute an instruction
• Fetch, Decode, Execute, Memory, Writeback

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State Elements

• State elements are needed to contain the state
  (value)
• Clocks used in synchronous logic
• When should an element that contains state be
  updated?
• Unclocked state element set-reset latch

(cycle time)
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D-latch vs. D flip-flop

• D-latch
• D flip-flop
• Output changes only on the clock edge

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Our Implementation

• An edge triggered methodology
• Typical execution
• Read contents of some state elements,
• Send values through some combinational logic
• Write results to one or more state elements

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The Steps of Designing a Processor

• 1. Instruction Set Architecture used for
  high-level specification or Register-Transfer
  Level (RTL) model
• Includes major organizational decisions
• Examples number and type of functional units,
  number of register file ports
• 2. Datapath-RTL refined to specify functional
  unit behavior and interfaces
• Datapath components
• Datapath interconnect
• Associated datapath control points
• 3. Control structure defined and Control-RTL
  behavioral representation created
• 4. RTL datapath and control design are refined to
  track physical design and functional validation
• Changes made for timing and bug fixes
• Amount of work varies with capabilities of CAD
  tools and degree of optimization for cost and
  performance

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Example RTL

• add rd, rs, rt
• Instruction ? memPC Fetch instruction from
  memory
• Rrd ? Rrs Rrt ADD operation
• PC ? PC 4 Calculate next address
• lw rt, imm16(rs)
• Instruction ? memPC Fetch instruction from
  memory
• Addr ? Rrs SignExt(imm16) Compute memory
  Addr
• Rrt ? MemAddr Load data into register
• PC ? PC 4 Calculate next address

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Combinational Logic Elements

• Combinational logic does not use a clock
• Adder
• MUX
• ALU

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Logic Abstraction

• Make sure you understand the abstractions!
• Simpler version is easier to understand than
  actual implementation

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Register File

• Built using D flip-flops
• Data ports
• Two read ports connected to two 32-bit buses
• One write port connected to on 32-bit bus
• Select register by
• Read register 1,
• Read register 2,
• Write register

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Register File Read Ports

• Two read ports
• Two source operands
• are read from two ports

Do you understand? What is the Mux above?
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Register File Write Port

• We still use the real clock to determine when to
  write

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Storage Element Memory

• Two ports and buses for memory
• One input bus (Data In) connected to one input
  port (Write data)
• One output bus (Data Out) connected to one output
  port (Read data)
• Memory word is selected by Address
• If MemRead 1 then
• Address selects the word to put on Data Out
• If MemWrite 1 then
• Address selects the memory word to be written
  via the Data In bus

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Instruction Fetch Unit

• Common RTL operations
• Fetch the Instruction
• Instruction ? memPC
• Update the program counter
• Sequential Code PC ? PC 4
• Branch and Jump PC ? something else

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R-type ALU Operations
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Load Store
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Branch
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Simple Implementation

• Include the functional units we need for each
  instruction

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Building the Datapath
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Control

• Selecting the operations to perform (ALU,
  read/write, etc.)
• Controlling the flow of data (multiplexor inputs)
• Information comes from the 32 bits of the
  instruction
• Example add 8, 17, 18
• ALU's operation based on instruction type and
  function code

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ALU Control

• What should the ALU do with this instruction
• Example lw 1, 100(2)
• ALU control input 0000 AND 0001 OR 0010 add 0
  110 subtract 0111 set-on-less-than 1100 NOR
• Why is the code for subtract 0110 and not 0011?

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ALU Control (contd)

• Must describe hardware to compute 4-bit ALU
  control input
• Given instruction type (opcode) decides the
  ALUOp ALUOp 00 (lw, sw
  instructions) 01 (beq instruction) 10 (all
  arithmetic-logical instructions)
• Function code is meaningful only for arithmetic
  type (10)
• Describe it using a truth table (can turn into
  gates)

Input bits
output bits
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Combinational Logic for ALU Control
00 (lw, sw instructions)01 (beq instruction) 10
(arithmetic-logical)
0000 AND0001 OR0010 add0110 subtract0111
slt1100 NOR
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Main Control

• Instruction encoding determines the main control
• Arithmetic-logical instructions add, sub,
  and, or, slt
• Memory instructions branch lw, sw, beq
• Jump instructions j

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Control
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Implementing Jump

• Unconditional jump to target address
• Target address is calculated by using
  pseudo-direct addressing
• PCnext (PC4)31-28 (Instruction25-0 ltlt 2)
• Additional logic to calculate the target address
  (Figure 5.24 in textbook)
• Reuse adder for PC4
• Extra shifter to calculate ltlt 2 operation
• Extra mux to select the target address

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Our Simple Control Structure

• All of the logic is combinational
• Wait for everything to settle down and right
  thing to be done
• ALU might not produce right answer right away
• We use write signals along with clock to
  determine when to write
• Cycle time determined by length of the longest
  path

We are ignoring some details like setup and hold
times
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Single Cycle Implementation (example)

• Calculate cycle time under the following
  condition
• Operation time of major units (assume no delay
  for the others)
• Memory (200ps), ALU and adders (100ps), Register
  file access (50ps)
• Compare with a machine with variable clock cycles
• Assume the following instruction mix
• load(25), store(10), ALU instr(45),
  branch(15), jump(5)

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Where we are headed

• Single Cycle Problems
• What if we had a more complicated instruction
  like floating point?
• Wasteful of area
• One Solution
• Use a smaller cycle time
• Have different instructions take different
  numbers of cycles
• A multicycle datapath