Universidade Federal de Santa Catarina

1
Universidade Federal de Santa Catarina Centro
Tecnológico Computer Science Electrical
Engineering
Digital Integrated Circuits INE 5442 / EEL 7312
Lectures 33 to 36 Combinational Circuits in CMOS
Prof. José Luís Güntzel guntzel_at_inf.ufsc.br
2
Agenda

• Complementary CMOS
• Pass-Transistor Logic

3
Combinational vs. Sequential Logic
Output values depend only on the current input
values (no feedback, no storage element).
Output values depend on the current input values
and on previous input values (feedback
with/without storage element).
4
Logic Families in CMOS

• Static CMOS Logic
• Complementary CMOS
• Ratioed Logic
• Pass-Transistor Logic
• Dynamic CMOS Logic

5
Metrics for Choosing a Gate Design/Family

• Area in silicon (related to number of
  transistors)
• Speed (propagation delay)
• Energy consumption/Power dissipation
• Robustness to noise
• Reliability
• Manufacturability

Depending on the application, the emphasis will
be on different metrics. (Rabaey Chandrakasan
Nikolic, 2005)
6
Static CMOS Logic

• Features
• Robustness (low sensitivity to noise).
• Good performance.
• Low power consumption (no static consumption,
  except for leakage currents).
• Easy to design (good for novice designers)

7
Complementary Logic the inverter
Logic-level symbol
Transistor schematics
in
out
Truth-table
in out
0 1
1 0
8
Complementary Logic mask layout for an inverter
Gnd
N channel
P channel
Vdd
N
N
P
P
P well
N Substrate
P-implant
N-implant
9
Complementary Logic the inverter
Steady-state operation
in out
0 1
1 0

• Transistors seemed as ideal electronic switches
• Capacitance represents the total charge at the
  gates output

10
Complementary Logic

• Pull-up and pull-down networks are mutually
  exclusive transistor associations (dual)
• In steady state, there is always a path to either
  Vdd or GND! (In steady state, the output is
  always a low-impedance node.)

11
Static CMOS Logic
Discharging the output capacitance
VGS
Charging the output capacitance
VGS
12
NMOS Series/Parallel Associations
control variables
X
control variables
A
B
Y
XY if A1 AND B1
XY if A1 OR B1
Problem NMOS transistors pass a weak 1 (but a
strong 0)
13
PMOS Series/Parallel Associations
control variables
control variables
X
A
B
Y
XY if A0 OR B0
XY if A0 AND B0
Problem PMOS transistors pass a weak 0 (but a
strong 1)
14
Complementary Logic

• Only negative logic functions are implemented
  (e.g. inverter, NAND, NOR, XNOR)
• Design procedure
• use the 0 of the gate function to design the
  pull-down network
• Apply De Morgans theorem to find the pull-up
  network.
• An n-input logic gate requires 2n transistors.

15
Complementary Logic 2-input Nand
Logic-level symbol
Transistor schematics
Truth-table
A B S
0 0 1
0 1 1
1 0 1
1 1 0
16
Complementary Logic 2-input Nand mask layout
A
B
Out
GND
17
Complementary Logic 2-input Nand
Steady state behavior 4 possible input
combinations
A B S
0 0 1
0 1 1
1 0 1
1 1 0
18
Complementary Logic 2-input Nand
Delay characterization through electric-level
simulation (e.g., Spice)
Evaluates the individual contribution of each
input (the others are kept at their
non-controlling values)
input tpLH (ps) tpHL (ps)
A
B
19
Complementary Logic 2-input Nand
A
B
Out
GND
20
Complementary Logic 2-input Nor
Logic-level symbol
Transistor schematics
Truth-table
A B S
0 0 1
0 1 0
1 0 0
1 1 0
21
Building Complementary CMOS Complex Gates
Example
S ABC

1. If the logic gate equation is not negated,
   imagine it as it were. At the end, an extra
   inverter will have to be added . (Alternatively,
   apply De Morgans theorem)
2. Take the non-inverting equation of the logic gate
   to design the pull-down network

S
B
A
C
22
Building Complementary CMOS Complex Gates
Example
S ABC

• Design the pull-up network by finding the dual of
  the pull-down network, already designed
• Each series NMOS association gives rise to a
  parallel PMOS association
• Each parallel NMOS association gives rise to a
  series PMOS association

23
Properties of Complementary CMOS Gates

• Full rail-to-rail swing high noise margins
  (VOHVdd , VOLGND)
• Logic levels not dependent upon the relative
  device sizes ratioless
• Always a path to Vdd or Gnd in steady state low
  output impedance
• Extremely high input resistance nearly zero
  steady-state input current
• No direct path steady state between power and
  ground no static power dissipation
• Propagation delay function of load capacitance
  and resistance of transistors

Source Rabaey Chandrakasan Nikolic, 2005
24
Switch Delay Models for Complementary Gates
NAND2
INV
NOR2
Source Rabaey Chandrakasan Nikolic, 2005
25
Delay Depends on the Input Pattern

• Delay is dependent on the pattern of inputs
• Low to high transition
• both inputs go low
• delay is 0.69 Rp/2 CL
• one input goes low
• delay is 0.69 Rp CL
• High to low transition
• both inputs go high
• delay is 0.69 2Rn CL

Source Rabaey Chandrakasan Nikolic, 2005
26
Delay Depends on the Input Pattern
NMOS 0.5?m/0.25 ?m PMOS 0.75?m/0.25 ?m CL
100 fF
Sized for tpLH tpHL
AB1?0
Entradas Atraso (ps)
AB0?1 69 ?
A1, B0?1 50 ?
A 0?1, B1 62 ?
AB1?0 35 ?
A1, B1?0 57 ?
A 1?0, B1 76 ?
A1 ?0, B1
Voltage V
A1, B1?0
time ps
Source Rabaey Chandrakasan Nikolic, 2005
27
Delay Depends on the Input Pattern
NMOS 0.5?m/0.25 ?m PMOS 0.75?m/0.25 ?m CL
100 fF
Sized for tpLH tpHL
AB1?0
A1 ?0, B1
Voltage V
A1, B1?0
time ps
Source Rabaey Chandrakasan Nikolic, 2005
28
The Body Effect

• The VT of the two NMOS transistors are calculate
  by

VTn2 Vtn0 ? (( 2?f Vint)0.5 (2?f)0.5)
M2
VTn1 Vtn0
int
M1
Source Rabaey Chandrakasan Nikolic, 2005
29
Transistor Sizing
Considering intra-cell capacitances
Distributed RC model (Elmore Delay) tpHL 0,69
? (R1? C1 (R1R2) ? C2 (R1R2R3) ? C3
(R1R2R3R4) ? CL) If R1R2R3R4 then tpHL
0.69 Reqn(C12C23C34CL)
30
Propagation Delay as a Function of Fan-In
Propagation delay of CMOS NAND gate
Gates with more than 4 inputs should be avoided
Source Rabaey Chandrakasan Nikolic, 2005
31
Propagation Delay as a Function of Fan-Out
tpNOR2
tpNAND2
All gates have the same drive current.
tpINV
tp (psec)
Slope is a function of driving strength
eff. fan-out
Source Rabaey Chandrakasan Nikolic, 2005
32
Propagation Delay as a Function of Fan-Out

• Fan-in quadratic due to increasing resistance
  and capacitance
• Fan-out each additional fan-out gate adds two
  gate capacitances to CL
• tp a1FI a2FI2 a3FO

Source Rabaey Chandrakasan Nikolic, 2005
33
Design Techniques for Static CMOS Gates

• Transistor sizing
• Desde que a capacitância de saída domine
• Progressive sizing

RC distribuído WM1 gt WM2 gt WM3 gt gt WMN (o
trans. mais próximo da saída tema a menor
resistência de canal.)
Pode reduzir o atraso da porta em até 20
(segundo Rabaey)
Source Rabaey Chandrakasan Nikolic, 2005
34
Design Techniques for Static CMOS Gates

• Transistor ordering

Critical path
Critical path
0?1
charged
In1
1
charged
In3
M3
M3
1
In2
1
In2
M2
charged
M2
charged
1
In3
In1
M1
charged
M1
charged
0?1
O Atraso é determinado pelo tempo para
descarregar CL
O Atraso é determinado pelo tempo para
descarregar CL, C1 e C2
Source Rabaey Chandrakasan Nikolic, 2005
35
Design Techniques for Static CMOS Gates

• Explorando a Decomposição Lógica

F ABCDEFGH
Elevando fanin (evitar)
Lógica de 2 níveis em CMOS
Faninlimitado a 2, fanout unitário
Source Rabaey Chandrakasan Nikolic, 2005
36
Design Techniques for Static CMOS Gates

• Isolamento de carga elevada usando buffer

Source Rabaey Chandrakasan Nikolic, 2005
37
Cell Design

• Standard Cells
• General purpose logic
• Can be synthesized
• Same height, varying width
• Datapath Cells
• For regular, structured designs (arithmetic)
• Includes some wiring in the cell
• Fixed height and width

Source Rabaey Chandrakasan Nikolic, 2005
38
Standard Cell Layout Methodology 1980s
Routing channel
VDD
signals
GND
Source Rabaey Chandrakasan Nikolic, 2005
39
Standard Cell Layout Methodology 1990s
Mirrored Cell
No Routing channels
VDD
VDD
M2
M3
GND
GND
Mirrored Cell
Source Rabaey Chandrakasan Nikolic, 2005
40
Standard Cells
N Well
Cell height 12 metal tracks Metal track is
approx. 3? 3? Pitch repetitive distance
between objects Cell height is 12 pitch
Out
In
2?
Rails 10?
GND
Cell boundary
Source Rabaey Chandrakasan Nikolic, 2005
41
Standard Cells
With silicided diffusion
With minimaldiffusionrouting
Out
In
Out
In
GND
GND
Source Rabaey Chandrakasan Nikolic, 2005
42
Standard Cells
2-input NAND gate
A
B
Out
GND
Source Rabaey Chandrakasan Nikolic, 2005
43
Stick Diagrams
Contains no dimensions Represents relative
positions of transistors
Inverter
NAND2
Out
Out
In
A
B
GND
GND
Source Rabaey Chandrakasan Nikolic, 2005
44
Stick Diagrams
Logic Graph
A
C
j
B
X C (A B)
C
i
A
B
A
B
C
Source Rabaey Chandrakasan Nikolic, 2005
45
Two Versions of C (A B)
C
A
B
A
B
C
VDD
VDD
X
X
GND
GND
Source Rabaey Chandrakasan Nikolic, 2005
46
Consistent Euler Path
X
C
VDD
i
X
A
B
j
A
B
C
GND
Source Rabaey Chandrakasan Nikolic, 2005
47
OAI22 Logic Graph
X
PUN
A
C
C
D
B
D
VDD
X
X (AB)(CD)
C
D
A
B
A
B
PDN
A
GND
B
C
D
Source Rabaey Chandrakasan Nikolic, 2005
48
Multi-Fingered Transistors
One finger
Two fingers (folded)
Less diffusion capacitance
Source Rabaey Chandrakasan Nikolic, 2005
49
Pass Transistor Logic
Exemplo 1 uma função arbitrária (com 4 vars. de
controle)
buffer
A B saída
0 0 E1
0 1 E1
1 0 E1
1 1 E2
Saída A?B?E2A?E1B?E1

• N transistores
• Sem consumo estático

50
O Comportamento do Transistor de Passagem
3.0
In
Out
2.0
x
Tensão V
1.0
0.0
0
0.5
1
1.5
2
Tempo ns

• Vx não consegue atingir Vdd, mas Vdd -VTn(Vx)
  (efeito de corpo)
• Tensão na entrada do inversor não é suficiente
  para desligar o transistor PMOS
• Mensagem não cascatear transistores de passagem,
  conectando-os a gates de outras estruturas
  similares.

Source Rabaey Chandrakasan Nikolic, 2005
51
NMOS-only Switch
V
C
2.5 V
C
2.5

M
2
A
2.5 V
B
A
2.5 V
M
n
B
M
C
1
L
does not pull up to 2.5V, but 2.5V -
V
V
TN
B
Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
Source Rabaey Chandrakasan Nikolic, 2005
52
NMOS Only Logic Level Restoring Transistor
V
DD
V
DD
Level Restorer
M
r
B
M
2
X
M
A
Out
n
M
1
Advantage Full Swing
Restorer adds capacitance, takes away pull down
current at X
Source Rabaey Chandrakasan Nikolic, 2005
Ratio problem
53
Restorer Sizing
3.0

• Upper limit on restorer size
• Pass-transistor pull-downcan have several
  transistors in stack

W
/
L
1.75/0.25
V
r
e
W
/
L
1.50/0.25
g
r
a
t
l
o
V
W
/
L
1.25/0.25
W
/
L
1.0/0.25
r
r
Time ps
Source Rabaey Chandrakasan Nikolic, 2005
54
Solution 2 Single Transistor Pass Gate with VT0
V
DD
V
DD
0V
2.5V
Out
0V
V
DD
2.5V
WATCH OUT FOR LEAKAGE CURRENTS
Source Rabaey Chandrakasan Nikolic, 2005
55
Complementary Pass Transistor Logic
Source Rabaey Chandrakasan Nikolic, 2005
56
Solution 3 Transmission Gate
C
C
A
A
B
B
C
C
C
2.5 V
A
2.5 V
B
C
L
C

0 V
Source Rabaey Chandrakasan Nikolic, 2005
57
Resistance of Transmission Gate
Source Rabaey Chandrakasan Nikolic, 2005
58
Pass-Transistor Based Multiplexer
S
VDD
GND
In1
In2
S
Source Rabaey Chandrakasan Nikolic, 2005
59
Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
Source Rabaey Chandrakasan Nikolic, 2005
60
Delay in Transmission Gate Networks
m
R
R
R
eq
eq
eq
In
C
C
C
C
(c)
Source Rabaey Chandrakasan Nikolic, 2005
61
Delay Optimization
Source Rabaey Chandrakasan Nikolic, 2005
62
Transmission Gate Full Adder
Similar delays for sum and carry
Source Rabaey Chandrakasan Nikolic, 2005