Aucun%20titre%20de%20diapositive

1
Hierarchical Conditional Dependency Graphs for
False Path Identification
A.Kountouris, C.Wolinski
2
Our New Co-design System Under Construction
3
Methodology used
High-level specification Hardware C, C, VHDL,
Signal

• Scheduling under constraints
• Hardware Resources Sharing
• False Path Detection

Final HCDG
Clock Calculation for each Path in CCFG
Conditional Control Flow Graph
Mutual Exclusiveness Detection Process
4
Hierarchical Conditional Dependency Graph
H6H4H5
5
JIAN Benchmark
process jian(a, b, c, d, e, f, g, x, y) in port
a8, b8, c8, d8, e8, f8, g8 in port
x, y out port u8, v8 static T1 static
T28, T38, T48, T58 T1 (a 1 b) lt
c T2 d 2 e T3 c 3 1 if (y)
if (T1) u T3 4 d
/u1 / else if (!x) u
T2 5 d /u2 / if (!T1 x)
v T2 6 e else T4
T3 7 e T5 T4 8 f u
T5 9 g /u3 /
Clocks
Operations
6
JIAN Benchmark
7
JIAN Benchmark
8
JIAN Benchmark
9
JIAN Benchmark
STOP
Clock Calculation for each Path
path1C01clockH1 OK
path1C01,C11clockH1H2 OK
path1C01,C11,C21clockH1H2H7 OK
path1C01,C11,C22clockH1H2H6 OK
path1C01,C11,C22clockH1H2H6 OK
path2C01,C11,C22,C31clockH1H2H7H9 OK
path1C01,C11,C22clockH1H2H6 OK
path2C01,C11,C22,C31clockH1H2H7H9 OK
path3CO1,C11,C21,C32clockH1H2H7H10 OK
path1C01,C12clockH1H3 OK
path1C01,C12clockH1H3 OK path2
C01,C11,C22,C41clockH1H2H6H9 NO path3
C01,C11,C22,C31,C41clockH1H2H7H9H9 OK
path4 CO1,C11,C21,C32,C41clockH1H2H7H10H9
NO
path1C01,C12clockH1H3 OK path2
C01,C11,C22,C41clockH1H2H6H9 NO path3
C01,C11,C22,C31,C41clockH1H2H7H9H9 OK
path4 CO1,C11,C21,C32,C41clockH1H2H7H10H9
NO path5 C01,C11,C22,C42clockH1H2H6H8
OK path6 C01,C11,C22,C31,C42clockH1H2H7H9H8
OK path7 CO1,C11,C21,C32,C42clockH1H2H7H10
H8 OK
path1C01,C12,C51clockH1H3 OK path2
C01,C11,C22,C31,C41 ,C51clockH1H2H7H9H9
OK path3 C01,C11,C22,C42 ,C51clockH1H2H6H8
OK path4 C01,C11,C22,C31,C42 ,C51clockH1H2H7
H9H8 OK path5 CO1,C11,C21,C32,C42
,C51clockH1H2H7H10H8 OK
10
JIAN Benchmark
Results
11
(No Transcript)