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3D-TV accelerator hardware
Real-time Depth Image Based Rendering Hardware
Accelerator for Advanced Three Dimensional
Television System (2006 IEEE International
Conference on Multimedia and Expo)? Tim van
den Kerkhof Michiel Rooijakkers
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Overview

• Introduction
• Complexity
• Hardware architecture
• Gaussian filter
• 3D image warping
• Layout specifications
• Advantages
• Disadvantages
• Conclusions

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Introduction
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Complexity
Optimized algorithm 7.08 GIPS Current Intel P4
CPU 3.80 GIPS (2006)? - Gaussian filter size 5
x 30px - Tradeoff between Image quality and
Hardware cost
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Hardware architecture
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Gaussian filter
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3D image warping
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Layout specifications
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Advantages

• Low power consumption
• Reduces bandwidth for television broadcast
• Feasable under current architecture constraints

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Disadvantages

• Introduction of holes and artifacts
• Clientside processing
• No on-chip holefilling

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Conclusions

• Technique optimized for cost reduction (33
  reduction of bandwidth)?
• Production ready
• Good holefill methods might lengthen technology
  lifetime
• Questions?