Chapter 7 Parallel Ports

1
Chapter 7Parallel Ports
2
Basic Concepts of I/O

• I/O devices are also called peripheral devices.
• I/O devices are pieces of equipment that exchange
  data with a computer.
• Examples include switches, light-emitting diodes,
  cathode-ray tube screens, printers, modems,
  keyboards, and disk drives.

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Interface (Peripheral) Chip (1 of 2)

• A chip whose function is to synchronize data
  transfer between the CPU and I/O devices
• Consists of control registers, status registers,
  data direction latches, and control circuitry
• Has pins that are connected to the CPU and I/O
  port pins that are connected to the I/O devices
• Each interface chip has a chip enable signal
  input or inputs, when asserted, allow the
  interface chip to react to the data transfer
  request.
• Data transfer between an I/O device and the CPU
  can be proceeded bit-by-bit or in multiple bits
  (parallel).

4
Interface (Peripheral) Chip (2 of 2)

• Address decoder makes sure that each time one and
  only one peripheral device responds to the CPUs
  I/O request.

5
I/O Schemes

• Isolated I/O scheme
• The microprocessor has dedicated instructions for
  I/O operations.
• The microprocessor has a separate address space
  for I/O devices.
• Memory-mapped I/O scheme
• The microprocessor uses the same instruction set
  to perform memory accesses and I/O operations.
• The I/O devices and memory components are
  resident in the same memory space.

6
I/O Transfer Synchronization

• The role of an interface chip
• Synchronizing data transfer between the CPU and
  the interface chip
• Synchronizing data transfer between the interface
  chip and the I/O device

7
Synchronizing the Microprocessor and the
Interface Chip

• The polling method
• For input -- The microprocessor checks a status
  bit of the interface chip to find out if the
  interface chip has received new data from the
  input device.
• For output -- The microprocessor checks a status
  bit of the interface chip to find out if it can
  send new data to the interface chip.
• The interrupt-driven method
• For input -- The interface chip interrupts the
  microprocessor whenever it has received new data
  from the input device.
• For output -- The interface chip interrupts the
  microprocessor whenever it can accept new data
  from the microprocessor.

8
Synchronizing the Interface Chip and the I/O
Devices

• Brute-force method -- useful when the data timing
  is unimportant
• For input -- Nothing special is done. The
  microprocessor reads the interface chip and the
  interface chip returns the voltage levels on the
  input port pins to the microprocessor.
• For output -- Nothing special is done. The
  interface chip places the data that it received
  from the microprocessor directly on the output
  port pins.
• The strobe method -- a strobe signal used to
  indicate that data are stable on I/O port pins
• For input -- The interface chip latches the data
  into its data register using the strobe signal.
• For output -- The interface chip places the data
  on port pins that it received from the
  microprocessor and asserts the strobe signal.
  The output device latches the data using the
  strobe signal.
• The handshake method -- used when timing is
  crucial
• Two handshake signals used to synchronize the
  data transfer. One signal, call it H1, is
  asserted by the interface chip. The other signal,
  call it H2, is asserted by the I/O device.
• Two handshake modes available
• Pulse mode and interlocked mode

9
Input Handshake Protocol

• Step 1. The interface chip asserts (or pulses) H1
  to indicate its intention to input data.
• Step 2. The input device puts data on the data
  port pins and also asserts (or pulses) the
  handshake signal H2.
• Step 3. The interface chip latches the data and
  de-asserts H1. After some delay, the input device
  also de-asserts H2.

10
Output Handshake Protocol

• Step 1. The interface chip places data on the
  port pins and asserts (or pulses) H1 to indicate
  that it has valid data to be output.
• Step 2. The output device latches the data and
  asserts (or pulses) H2 to acknowledge the receipt
  of data.
• Step 3. The interface chip de-asserts H1
  following the assertion of H2. The output device
  then de-asserts H2.

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Overview of HCS12 Parallel Ports (1 of 3)

• The HCS12 members have from 48 to 144 I/O pins
  arranged in 3 to 12 ports and packaged in a quad
  flat pack (QFP) or low profile quad flat pack
  (LQFP).
• All I/O pins serve multiple functions.
• When a peripheral function is enabled, its
  associated pins cannot be used as I/O pins.
• Each I/O port has several registers to support
  its operation.
• Registers related to I/O ports have been assigned
  a mnemonic name and the user can use these names
  to refer to them
• movb FF,PTA output FF to Port A

12
Overview of HCS12 Parallel Ports (2 of 3)

• All I/O ports (except PAD0 and PAD1) have an
  associated data direction register and a data
  register.
• The name of the data direction register is formed
  by adding the letters DDR as the prefix to the
  port name. For example, DDRA, DDRB, and DDRT.
• To configure a pin for output, write a 1 to the
  associated bit in the data direction register.
• To configure a pin for input, write a 0 to the
  associated bit in the data direction register.
• movb FF,DDRA configure port A for output
• movb 0,DDRA configure port A for input
• bset DDRA,81 configure Port A pin 7 and 1 for
  output

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Overview of HCS12 Parallel Ports (3 of 3)

• The name of port data register is formed by
  adding letters PT as the prefix to the port
  name. For example, PTA, PTB, PTP, and PTT.
• We can also use PORT as the prefix to the port
  name for port A, B, E, and K.
• Output a value to a port is done by storing that
  value to the port data register.
• movb FF,DDRH configure Port H for output
• movb 37,PTH output the hex value 37 to port H
• Input a value from an input port is done by
  loading from the port data register.
• movb 0,DDRH configure Port H for input
• ldaa PTH read data from port H into A
• An I/O port may have up to eight associated
  registers.

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Port A and Port B

• In expanded mode, Port A carries the
  time-multiplexed higher address/data signals
  A15/D15A8/D8.
• In expanded mode, Port B carries the
  time-multiplexed lower address/data signals
  A7/D7A0/D0.
• In single chip mode, these two ports are used as
  general I/O ports.

15
Port E

• Port E pins are used for bus control and
  interrupt service request signals.
• When a Port E pin is not used as control or
  interrupt signal, it can be used as general I/O
  pin.

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Port E Registers

• Port E assignment register (PEAR)
• In expanded mode, the PEAR register assigns the
  function of each port E pin.
• MODE register
• This register establishes the operation mode and
  other miscellaneous functions.
• Pull-up control register (PUCR)
• This register selects the pull-up resistors for
  the pins associated with the core ports.
• Port A, B, E, and K are in the core part.
• Reduced drive register (RDRIV)
• This register selects reduced drive for the pins
  associated with the core ports.
• This gives reduced power consumption and reduced
  RFI with a slight increase in transition time.
• External bus interface control register (EBICTL)
• Only bit 0 is implemented (ESTR).
• The ESTR bit enables/disables the E clock
  stretching.

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Port K

• Has PTK and DDRK registers
• Carries expanded address XADDR14XADDR19 in
  expanded mode
• On the rising edge of the RESET signal, the value
  of the PK7 pin is latched into the ROMON bit of
  the MISC register in expanded mode. If it is 1,
  the on-chip flash memory is enabled.
• ROMON is forced to 1 in single chip mode.

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Port T

• Has Port T data register (PTT), Port T data
  direction register (DDRT), Port input register
  (PTIT), reduced drive register (RDRT), pull
  device enable register (PERT), and port polarity
  select register (PPST)
• The PTIT register allows the user to read back
  the status of Port T pins.
• The RDRT register can configure the drive
  strength (current output) of each port pin as
  either full or reduced load.
• The PERT register is used to enable an input Port
  T pin pull-up or pull-down device.
• The PPST register selects whether a pull-down or
  pull-down device is connected to the pin.
• Port T pins are also used as timer input
  capture/output compare pin.

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Port S

• Port S pins are used as general I/O, serial
  communication interface, and serial peripheral
  interface pins.
• Port S has a Port S wired-or mode register (WOMS)
  in addition to all registers associated with Port
  T.

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Port M

• Port M has all the equivalent registers that Port
  S has and also a module routing register (MODRR).
  
• The MODRR configures the rerouting of CAN0, CAN4,
  SPI0, SPI1, and SPI2 on defined port pins.

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• Example 7.1 Give an instruction to configure the
  MODRR register to achieve the following port
  routing
• 1. CAN0 use pins PM1 and PM0
• 2. CAN1 use pins PM3 and PM2
• 3. CAN2 use pins PM5 and PM4
• 4. CAN3 use pins PM7 and PM6
• 5. I2C use PJ7 and PJ6
• 6. SPI0 use pins PS7PS4
• 7. SPI1 use pins PH3PH0
• 8. SPI2 use pins PH7PH4
• Solution This routing requirement can be
  achieved by preventing CAN4 from using any port
  pins and keep the default routing after reset.
• The following instruction will satisfy the
  requirement
• movb 60,MODRR CAN4 must be disabled

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• Example 7.2 Give an instruction to configure the
  MODRR register to achieve the following port
  routing
• 1. CAN0 use pins PM1 and PM0
• 2. CAN1 use pins PM3 and PM2
• 3. CAN2 disabled
• 4. CAN3 disabled
• 5. I2C use PJ7 and PJ6
• 6. SPI0 use pins PS7PS4
• 7. SPI1 use pins PP3PP0
• 8. SPI2 use pins PH7PH4
• Solution This routing requirement can be
  satisfied by the following instruction
• movb 40,MODRR CAN2CAN4 must be disabled

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Port H, J, and P

• These three I/O ports have the same set of
  registers
• Port I/O register (PTH, PTJ, PTP)
• Port Input Register (PTIH, PTIJ, PTIP)
• Port Data Direction Register (DDRH, DDRJ, DDRP)
• Port Reduced Drive Register (RDRH, RDRJ, RDRP)
• Port Pull Device Enable Register (PERH, PERJ,
  PERP)
• Port Polarity Select Register (PPSH, PPSJ, PPSP)
• Port Interrupt Enable Register (PIEH, PIEJ, PIEP)
• Port Interrupt Flag Register (PIFH, PIFJ, PIFP)
• These ports have edge-triggered interrupt
  capability in the wired-OR fashion.
• The SPI function pins can be rerouted to Port H
  and P.
• The interrupt edges can be rising or falling and
  are programmed through Port Device Enable
  Register and Port Polarity Select Register.
• The Port Interrupt Register allows the user to
  enable interrupts on these three ports.

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Port AD0 and AD1

• Many HCS12 devices have two 8-channel A/D
  converters (AD0 and AD1).
• Device that has only one 8-channel module is
  referred to as AD.
• When A/D functions are disabled, these two ports
  can be used as general input port.
• These two ports do not have data direction
  registers.
• Each module has a Digital Input Enable Register.
  In order to use an A/D pin as a digital input,
  one needs to set its associated bit in this
  register.

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Electrical Characteristic Consideration for I/O
Interfacing

• When interfacing I/O device to the MCU, one needs
  to consider electrical compatibility issues.
• There are two electrical compatibility issues
• Voltage level compatibility
• Current drive capability
• There are many IC technologies in use. Some are
  bipolar, whereas others are unipolar (mainly CMOS
  and BICMOS).
• Voltage parameters related to electrical
  compatibility
• Input high voltage (VIH)
• Input low voltage (VIL)
• Output high voltage (VOH)
• Output low voltage (VOL)

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For Device X to Drive Device Y Correctly

• The output high voltage of device X (VOHX) must
  be higher than the input high voltage of device Y
  (VIHY).
• The output low voltage of device X (VOLX) must be
  lower than the input low voltage of device Y
  (VILY).
• The input and output voltage levels of several
  popular logic families are shown in Table 7.3.
• At the same power supply level, the CMOS device
  has no problem in driving the bipolar and CMOS
  devices.
• Bipolar devices have problem in driving CMOS
  devices.
• HCS12 cannot be driven by bipolar devices.
• Bipolar devices have problems driving CMOS
  devices (including HCS12).

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Current Drive Capability

• The device that drives other devices must have
  enough sourcing (supply current) and sinking
  (absorb current) capability.
• Current flows out from the driving device when
  the driving voltage is high.
• Current flows into the driving device when the
  driving voltage is low.
• The driving device must be able to supply (or
  sink) enough current needed by those devices
  being driven for proper operation.
• If a device cannot source or sink enough current,
  then using buffer device is a common solution.
• The current capabilities of a logic device are
  determined by the following currents
• Input high current (IIH)
• Input low current (IIL)
• Output high current (IOH)
• Output low current (IOL)
• The current capability of several logic chip
  families are shown in Table 7.4.

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1. The IOH of an output pin must be equal to or
larger than the total current flowing into all
the peripheral pins that are connected to this
pin. 2. The IOL of an output pin must be equal to
or larger than the total current flowing out from
all the peripheral pins that are connected to
this pin.
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Timing Compatibility

• There is no timing problem when driving a
  peripheral pin that does not contain latches or
  flip-flops.
• When driving a latch or flip-flop device, one
  needs to make sure that the data set up time
  (tSU) and data hold time (tHD) are both
  satisfied.
• The data setup time and data hold time
  requirements are illustrated in Figure 7.28.

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Interfacing with LED Devices

• Figure 7.29 suggests three methods for
  interfacing with LEDs.
• Circuit (a) and (b) are recommended for LEDs that
  need only small current to light.
• Circuit (c) is recommended for LEDs that need
  larger current to light.

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• Example 7.3 Use Port B to drive eight LEDs using
  the circuit shown in Figure 7.30. Light each LED
  for half a second in turn and repeat assuming the
  HCS12 has a 24-MHz E clock.

- To turn on one LED at a time for half a second
in turn, one should output the value 80, 40,
20, 10, 08,04,02, and 01 and stay for half
a second in each value.
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The assembly program that performs the operation
is as follows include "C\miniide\hcs12.inc"
org 1500 movb FF,DDRB configure port B for
output bset DDRJ,02 configure PJ1 pin for
output bclr PTJ,02 enable LEDs to
light forever ldaa 16 initialize loop count to
8 ldx led_tab use X as the pointer to LED
pattern table led_lp movb 1,x,PTB turn on one
LED ldy 5 wait for half a second jsr delayby1
00ms " dbne a,led_lp reach the end of the
table yet? bra forever start from
beginning led_tab dc.b 80,40,20,10,08,04,02
,01 dc.b 01,02,04,08,10,20,40,80 inclu
de "C\miniide\delay.asm" end
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The C language version of the program is as
follows include "c\egnu091\include\hcs12.h" i
nclude "c\egnu091\include\delay.c" main
(void) char led_tab8
0x80,0x40,0x20,0x10,0x08,0x04,0x02,0x01,
0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80
char i DDRB 0xFF / configure port B
for output / DDRJ 0x02 / configure PJ1 pin
for output (needed for DRAGON12 board only)
/ PTJ 0xFD / enable LEDs to light (needed
for DRAGON12 board only)/ while (1)
for (i 0 i lt 16 i)
PTB led_tabi
delayby100ms(5)
return 0
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Driving a Single Seven-Segment Display

• A common cathode seven-segment display is driven
  by the 74HC244 via resistors.
• The output high voltage of the 74HC244 is close
  to 5V with a 5V power supply.
• The segment patterns for 0 to 9 are shown in
  Table 7.5.

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Driving Multiple Seven-Segment Displays

• Time multiplexing technique is often used to
  drive multiple displays in order to save I/O
  pins.
• One parallel port is used to drive the segment
  pattern and the other port turns on one display
  at a time. Each display is turned on and then off
  many times within a second. The persistence of
  vision make us feel that all displays are turned
  on simultaneously.

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• Example 7.4 Write a sequence of instructions to
  display 4 on the seven-segment display 4 in
  Figure 7.32.
• Solution To display the digit 4 on the display
  4, we need to
• Output the hex value 33 to port B
• Set the PK4 pin to 1
• Clear pins PK5 and PK3...P0 to 0

include lthcs12.incgt four equ 33
seven-segment pattern of digit 4 movb 3F,DDRK
configure PORT K for output movb FF,DDRB
configure PORT B for output bset PTK,10 turn
on seven-segment display 4 bclr PTK,2F turn
off seven-segment displays 5, 30 movb four,P
TB output the seven-segment pattern to
PORTP In C language DDRK 0x3F DDRB
0xFF PTK 0x10 PTB 0x33
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• Example 7.5 Write a program to display 123456 on
  the six seven-segment displays shown in Figure
  7.32.
• Solution Display 123456 on display 5, 4, 3,
  2, 1, and 0, respectively.
• The values to be output to Port B and Port K to
  display one digit at a time is shown in Table 7.6.

- The program logic is shown in Figure 7.33.
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include "c\miniide\hcs12.inc" pat_port equ PTB
Port that drives the segment
pattern pat_dir equ DDRB direction register of
the segment pattern sel_port equ PTK Port that
selects the digit sel_dir equ DDRK data
direction register of the digit select
port org 1500 movb FF,pat_dir configure
pattern port for output movb 3F,sel_dir
configure digit select port for
output forever ldx disp_tab use X as the
pointer loop movb 1,x,pat_port output digit
pattern and move the pointer movb 1,x,sel_port
output digit select value and move the
pointer ldy 1 wait for 1 ms jsr delayby1ms
cpx disp_tab12 reach the end of the
table bne loop bra forever include
"c\miniide\delay.asm" disp_tab dc.b 30,20
seven-segment display table dc.b 6D,10 dc.b 7
9,08 dc.b 33,04 dc.b 5B,02 dc.b 5F,01 e
nd
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include c\egnu091\include\hcs12.h include
c\egnu091\include\delay.c define pat_port
PTB / segment pattern port / define
pat_dir DDRB / pattern port data
direction register / define sel_port PTK
/ digit select port / define sel_dir DDRK
/ digit select port direction register
/ main (void) char disp_tab62
0x30,0x20,0x6D,0x10,0x79,0x08,
0x33,0x04,0x5B,0x02,0x5F,0
x01 char i pat_dir 0xFF /
configure pat_port for output / sel_dir
0x3F / configure sel_port for output /
while (1) for (i 0 i lt 6
i) pat_port
disp_tabi0 / output the segment pattern
/ sel_port disp_tabi1
/ turn on the display /
delaybyms(1) / wait for 1 ms
/ return 0
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Liquid Crystal Display (LCD) (1 of 2)

• The basic construction of an LCD is illustrated
  in Figure 7.34.
• The most common type of LCD allows the light to
  pass through when activated.
• An LCD segment is activated when a low frequency
  bipolar signal in the range of 30 Hz to 1KHz is
  applied to it.
• LCD can display characters and graphics.
• LCDs are often sold in a module with LCDs and
  controller unit built in.
• The Hitachi HD44780 is the most popular LCD
  controller being used today.

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Liquid Crystal Display (LCD) (2 of 2)
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A HD44780-Based LCD Kit (1 of 3)

• Display capability 4 x 20
• Uses the HD44780 as the controller as shown in
  Figure 7.35.
• Pins DB7DB0 are used to exchange data with the
  CPU.
• E input should be connected to one of the address
  decoder output or I/O pin.
• The RS signal selects instruction register (0) or
  data register (1).
• The VEE signal allows the user to adjust the LCD
  contrast.
• The HD44780 can be configured to display 1-line,
  2-line, and 4-line information.
• The pin assignment for character-based LCD module
  with less than and more than 80 characters are
  shown in Table 7.7 and 7.8.

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A HD44780-Based LCD Kit (2 of 3)
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A HD44780-Based LCD Kit (3 of 3)
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HD44780 Commands (1 of 4)
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HD44780 Commands (2 of 4)
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HD44780 Commands (3 of 4)

• The HD44780 has a display data RAM (DDRAM) to
  store data to be displayed on the LCD.
• The address range of DDRAM for 1-line, 2-line,
  and 4-line LCDs are shown in Table 7.11a, 7.11b,
  and 7.11c.
• The HD44780 has a character generator ROM that
  can generates 5 ? 8 or 5 ? 10 character patterns
  from a 8-bit code.
• The user can rewrite character patterns into the
  character generator RAM (CGRAM).
• Up to eight 5 ? 8 patterns or four 5 ? 10
  patterns can be programmed.

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HD44780 Commands (4 of 4)
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Registers of HD44780

• The HD44780 has two 8-bit user accessible
  registers instruction register (IR) and data
  register (DR).
• To write data into display data RAM or character
  generator RAM, the MCU writes into the DR
  register.
• The address of the data RAM should be set up with
  a previous instruction.
• The DR register is also used for data storage
  when reading data from DDRAM or CGRAM.
• The register selection is shown in Table 7.12.
• The HD44780 has a busy flag that is output from
  the DB7 pin.
• The HD44780 uses a 7-bit address counter to keep
  track of the address of the next DDRAM or CGRAM
  location to be accessed.

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HD44780 Instructions (1 of 3)

• Clear display
• Writes 0x20 (space character) to all DDRAM
  locations
• Sets 0 to the address counter (return cursor to
  upper left corner of the LCD)
• Sets increment mode
• Return home
• Sets address counter to 0
• DDRAM contents not changed
• Entry mode set
• Sets incrementing or decrementing of the DDRAM
  address
• Controls the shifting (shifts if S bit 1) of
  the display
• Display on/off control
• Turns on/off display
• Turns on/off cursor
• Turns on/off cursor blinking

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HD44780 Instructions (2 of 3)

• Cursor or display shift
• This function shifts the cursor position to the
  right or left without writing or reading display
  data.
• The shifting is controlled by two bits as shown
  in Table 7.13.
• Function set
• Sets the interface length (DL bit) to be 4- or
  8-bit
• Selects the number of lines (N bit) to be one or
  two lines
• Selects character font (F bit) to be 5 ? 8 or 5 ?
  10

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HD44780 Instructions (3 of 3)

• Set CGRAM address
• This command contains the address to be written
  into the address counter.
• Set DDRAM address
• This command allows the user to set the starting
  address to display information.
• Read busy flag and address
• This command reads the busy flag and the address
  counter.
• User can use this command to determine the LCD
  controller is ready to accept another command.
• User can use this command to control where to
  start displaying information.

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Interfacing the HD44780 with the HCS12

• One can treat the LCD kit as an I/O device and
  use an I/O port and several other I/O pins as
  control signals.
• The interface can be 4 bits or 8 bits.
• To read or write the LCD successfully, one must
  satisfy the timing requirements of the LCD. The
  timing diagrams for read and write are shown in
  Figure 7.37 and 7.38.

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• Procedure to send a command to the IR register
• Step 1
• Pull the RS and the E signals to low.
• Step 2
• Pull the R/W signal to low.
• Step 3
• Pull the E signal to high.
• Step 4
• Output data to the output port attached to the
  LCD data bus. One needs to configure the I/O Port
  for output before writing data to the LCD kit.
• Step 5
• Pull the E signal to low and make sure that the
  internal operation is complete.

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• The procedure for writing a byte to the LCD data
  register
• Step 1
• Pull the RS signal to high.
• Step 2
• Pull the R/W signal to low.
• Step 3
• Pull the E signal to high.
• Step 4
• Output data to the I/O port attached to the LCD
  data bus.
• Step 5
• Pull the E signal to low and make sure that the
  internal operation is complete.
• These procedures need to be repeated once for an
  LCD kit with 4-bit interface.

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• Write a function to send a command to the LCD kit
• Most LCD commands are completed in 40 ms.
• If the function waits for 40 ms after performing
  the specified operation, then most commands will
  be completed when the function returns.
• The assembly code for the 8-bit interface is as
  follows

lcdPort equ PTH LCD data port
lcdCtl equ PTK LCD control port lcdE
equ 80 E signal pin (PK7) lcdRW equ 20
R/W signal pin (PK5) lcdRS equ 10
RS signal pin (PK4) the command is contained in
A cmd2lcd bclr lcdCtl,lcdRSlcdRW select
instruction register and Write bset
lcdCtl,lcdE pull the E signal high staa
lcdPort send the command, along with RS, E
signals nop nop bclr lcdCtl,lcdE pull
the E signal low bset lcdCtl,lcdRW pull R/W to
high ldy 1 adding this delay will complete
the internal jsr delayby50us operation for
most instructions rts
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• The function to configure LCD sends four commands
  to the LCD kit
• Entry mode set
• Display on/off
• Function set
• Clear display

lcdDIR equ DDRH lcdCtlDIR equ DDRK openlcd
movb FF,lcdDIR configure port H for
output bset lcdCtlDir,B0 configure control
pins for output ldy 5 wait for LCD to
complete internal jsr delayby100ms
configuration ldaa 38 set 8-bit
data, 2-line display, 5x8 font jsr cmd2lcd
" ldaa 0F turn on
display, cursor, and blinking jsr cmd2lcd
" ldaa 06 move
cursor right (entry mode set instruction) jsr
cmd2lcd " ldaa 01
clear LCD screen and return to home
position jsr cmd2lcd " ldy
2 wait until "clear display"
command is complete jsr delayby1ms
" rts
69

• Function to output a character to the LCD
• The character to be output is in accumulator A.

putc2lcd bset lcdCtl,lcdRS select LCD Data
register bclr lcdCtl,lcdRW enable write to
LCD bset lcdCtl,lcdE pull E to high staa
lcdPort send data to LCD nop
provide enough length to E
signal nop " bclr
lcdCtl,lcdE pull the E signal low bset
lcdCtl,lcdRW pull R/W high to complete the
write cycle ldy 1 wait until the write
operation is jsr delayby50us complete rts
70

• Function to output a string terminated by a NULL
  character
• The string to be output is pointed to by index
  register X.
• Example 7.7 Write an assembly program to test the
  previous four subroutines by displaying the
  following messages on two lines
• hello world!
• I am ready!

puts2lcd ldaa 1,x get one character from
the string beq done_puts reach NULL
character? jsr putc2lcd bra
puts2lcd done_puts rts
71
include "hcs12.inc" lcdPort equ PTH LCD
data pins (PH7PH0) lcdDIR equ DDRH LCD
data direction port lcdCtl equ PTK LCD control
port lcdCtlDir equ DDRK LCD control port
direction lcdE equ 80 E signal
pin lcdRW equ 20 R/W signal pin lcdRS equ
10 RS signal pin org 1500 lds
1500 set up stack pointer jsr openlcd
initialize the LCD ldx msg1lcd jsr
puts2lcd ldaa C0 move to the second
row jsr cmd2lcd " ldx msg2lcd jsr
puts2lcd swi msg1lcd fcc "hello
world!" dc.b 0 msg2lcd fcc "I am
ready!" dc.b 0 include c\miniide\delay.asm"
include delay routines here
include the previous four LCD functions
72
define lcdPort PTH / Port H drives LCD
data pins / define lcdDIR DDRH /
Direction of LCD port / define lcdE 0x80
/ E signal (PK7) / define lcdRW 0x20
/ R/W signal (PK5) / define lcdRS 0x10
/ RS signal (PK4) / define lcdCtlDIR DDRK
/ LCD control port direction / void
cmd2lcd (char cmd) void openlcd (void) void
putc2lcd (char cx) void puts2lcd (char
ptr) void cmd2lcd (char cmd) char
temp char xa, xb lcdCtl
(lcdRSlcdRW) / select instruction register
pull R/W low / lcdCtl lcdE /
pull E signal to high / lcdPort cmd
/ output command / xa 1
/ dummy statements to lengthen E / xb
2 / " /
lcdCtl lcdE / pull E signal to low
/ lcdCtl lcdRW / pull R/W to
high / delayby50us(1) / wait until
the command is complete /
73
void openlcd(void) lcdDIR 0xFF
/ configure lcdPort port for output /
lcdCtlDIR 0xB0 / configure LCD control
pins for output / delayby100ms(5) /
wait for LCD to become ready / cmd2lcd
(0x38) / set 8-bit data, 2-line display,
5x8 font / cmd2lcd (0x0F) / turn
on display, cursor, blinking / cmd2lcd
(0x06) / move cursor right /
cmd2lcd (0x01) / clear screen, move
cursor to home / delayby1ms (2) /
wait until "clear display" command is complete
/
74
void putc2lcd(char cx) char temp
char xa, xb lcdCtl lcdRS / select
LCD data register and pull R/W high/ lcdCtl
lcdRW / pull R/W to low / lcdCtl
lcdE / pull E signal to high /
lcdPort cx / output data byte /
xa 1 / create enough width
for E / xb 2 / create
enough width for E / lcdCtl lcdE /
pull E to low / lcdCtl lcdRW / pull R/W
signal to high / delayby50us(1) void
puts2lcd (char ptr) while (ptr)
putc2lcd(ptr) ptr
75

• Write a C program to test the SSE256 LCD
  functions.

include "c\egnu091\include\hcs12.h" include
"c\egnu091\include\delay.c" include
c\egnu091\include\lcd_util_SSE256.c main
(void) char msg1 "hello world!"
char msg2 "I am ready!"
openlcd() cmd2lcd(0x80) / move cursor to the
1st column of row 1 / puts2lcd(msg1)
cmd2lcd(0xC0) / move cursor to 2nd
row, 1st column / puts2lcd(msg2)
return 0
76
Interfacing with DIP Switches (1 of 2)

• Switches are often grouped together. It is most
  common to have four or eight switches in a DIP
  package.
• DIP switches are often used to provide setup
  information to the microcontroller. After power
  is turned on, the microcontroller reads the
  settings of the DIP switches and performs
  accordingly.

77
Interfacing with DIP Switches (2 of 2)

• Example 7.9 Write a sequence of instructions to
  read the value from an eight-switch DIP connected
  to PORTA of the HCS12 into accumulator A.
• Solution

include c\miniide\hcs12.inc movb 0,DDRA
configure Port A for input ldaa PTA read Port
A In C language include c\egnu091\include\hcs
12.h void main () char xx DDRA 0 xx
PTA
78
Interfacing to a Keyboard

• A keyboard is arranged as an array of switches,
  which can be mechanical, membrane, capacitors, or
  Hall-effect in construction.
• Mechanical switches are most popular for
  keyboards.
• Mechanical switches have a problem called contact
  bounce. Closing a mechanical switch generates a
  series of pulses because the switch contacts do
  not come to rest immediately.
• In addition, a human cannot type more than 50
  keys in a second. Reading the keyboard more than
  50 times a second will read the same key stroke
  too many times.
• A keyboard input is divided into three steps
• Scan the keyboard to discover which key has been
  pressed.
• Debounce the keyboard to determine if a key is
  indeed pressed. Both hardware and software
  approaches for key debouncing are available.
• Lookup the ASCII table to find out the ASCII code
  of the pressed key.

79
Hardware Debouncing Techniques

• SR latches
• Non-inverting CMOS gates
• Integrating debouncer

80
Software Debouncing Technique

• The most popular and simple one has been the wait
  and see method.
• In this method, the program simply waits for
  about 10 ms and reexamines the same key again to
  see if it is still pressed.

81
ASCII Code Table Lookup

• The ASCII code of each key can be stored in a
  table for easy look up.

82
Interfacing the HCS12 to a Keypad

• A keypad usually consists of 12 to 24 keys and is
  adequate for many applications.
• Like a keyboard, a keypad also needs debouncing.
• A 16-key keypad can be easily interfaced to one
  of the HCS12 parallel ports.
• A circuit that interfaces a 16-key keypad is
  shown in Figure 7.41. In this Figure, pins
  PA7..PA4 each control four keys.

83

• Example 7.10 Write a program to perform keypad
  scanning, debouncing, and returns the ASCII code
  in accumulator A to the caller.
• Solution
• Pins PA4..PA7 each control one row of four keys.
• Scanning is performed by setting one of the
  PA7..PA4 pins to low, the other three pins to
  high and testing one key at a time.

include c\miniide\hcs12.inc" keyboard equ PTA
  get_char movb F0,DDRA set PA7PA4 for
output, PA3PA0 for input scan_r0 movb EF,keyboa
rd scan the row containing keys
0123 scan_k0 brclr keyboard,01,key0 is key 0
pressed? scan_k1 brclr keyboard,02,key1 is key
1 pressed? scan_k2 brclr keyboard,04,key2 is
key 2 pressed? scan_k3 brclr keyboard,08,key3
is key 3 pressed? bra scan_r1 key0 jmp db_key0
key1 jmp db_key1
84
key2 jmp db_key2 key3 jmp db_key3 scan_r1 movb D
F,keyboard scan the row containing keys
4567 scan_k4 brclr keyboard,01,key4 is key 4
pressed? scan_k5 brclr keyboard,02,key5 is key
5 pressed? scan_k6 brclr keyboard,04,key6 is
key 6 pressed? scan_k7 brclr keyboard,08,key7
is key 7 pressed? bra scan_r2 key4 jmp db_key4 ke
y5 jmp db_key5 key6 jmp db_key6 key7 jmp db_key7 s
can_r2 movb BF,keyboard scan the row
containing keys 89AB bclr keyboard,40
scan_k8 brclr keyboard,01,key8 is key 8
pressed? scan_k9 brclr keyboard,02,key9 is key
9 pressed? scan_kA brclr keyboard,04,keyA is
key A pressed? scan_kB brclr keyboard,08,keyB
is key B pressed? bra scan_r3 key8 jmp db_key8 ke
y9 jmp db_key9
85
keyA jmp db_keyA keyB jmp db_keyB scan_r3 movb 7
F,keyboard scan the row containing keys
CDEF scan_kC brclr keyboard,01,keyC is key C
pressed? scan_kD brclr keyboard,02,keyD is key
D pressed? scan_kE brclr keyboard,04,keyE is
key E pressed? scan_kF brclr keyboard,08,keyF
is key F pressed? jmp scan_r0 keyC jmp db_keyC ke
yD jmp db_keyD keyE jmp db_keyE keyF jmp db_keyF
debounce key 0 db_key0 jsr delay10ms brclr keybo
ard,01,getc0 jmp scan_k1 getc0 ldaa 30
return the ASCII code of 0 rts debounce key 1
86
db_key1 jsr delay10ms brclr keyboard,02,getc1 j
mp scan_k2 getc1 ldaa 31 return the ASCII
code of 1 rts db_key2 jsr delay10ms brclr keyboa
rd,04,getc2 jmp scan_k3 getc2 ldaa 32
return the ASCII code of 2 rts db_key3 jsr delay1
0ms brclr keyboard,08,getc3 jmp scan_r1 getc3 l
daa 33 return the ASCII code of
3 rts db_key4 jsr delay10ms brclr keyboard,01,g
etc4
87
jmp scan_k5 getc4 ldaa 34 return the ASCII
code of 4 rts db_key5 jsr delay10ms brclr keyboa
rd,02,getc5 jmp scan_k6 getc5 ldaa 35
return the ASCII code of 5 rts db_key6 jsr delay1
0ms brclr keyboard,04,getc6 jmp scan_k7 getc6 l
daa 36 return the ASCII code of
6 rts db_key7 jsr delay10ms brclr keyboard,08,g
etc7 jmp scan_r2
88
getc7 ldaa 37 return the ASCII code of
7 rts db_key8 jsr delay10ms brclr keyboard,01,g
etc8 jmp scan_k9 getc8 ldaa 38 return the
ASCII code of 8 rts db_key9 jsr delay10ms brclr
keyboard,02,getc9 jmp scan_kA getc9 ldaa 39
return the ASCII code of 9 rts db_keyA jsr delay
10ms brclr keyboard,04,getcA jmp scan_kB getcA
ldaa 41 get the ASCII code of A rts
db_keyB jsr delay10ms brclr keyboard,08,getcB j
mp scan_r3 getcB ldaa 42 get the ASCII code
of B rts
89
db_keyC jsr delay10ms brclr keyboard,01,getcC j
mp scan_kD getcC ldaa 43 get the ASCII code
of C rts db_keyD jsr delay10ms brclr keyboard,0
2,getcD jmp scan_kE getcD ldaa 44 get the
ASCII code of D rts
db_keyE jsr delay10ms brclr keyboard,04,getcE j
mp scan_kF getcE ldaa 45 get the ASCII code
of E rts db_keyF jsr delay10ms brclr keyboard,0
8,getcF jmp scan_r0 getcF ldaa 46 get the
ASCII code of F rts
90
delay10ms movb 90,TSCR1 enable TCNT fast
flags clear movb 06,TSCR2 configure
prescale factor to 64 movb 01,TIOS enable
OC0 ldd TCNT addd 3750 start an output
compare operation std TC0 with 10 ms time
delay wait_lp2 brclr TFLG1,01,wait_lp2 rts
91
The AD7302 D/A Converter (1 of 2)

• A dual-channel 8-bit D/A converter made by Analog
  Devices
• The AD7302 converts an 8-bit digital value into
  an analog voltage.
• The block diagram is shown in Figure 7.43. The
  AD7302 is designed to be a memory-mapped device.
  The CS signal must be low for this chip to work.
• The AD7302 needs a reference voltage to operate.
  The reference voltage could be external one (from
  the REFIN pin) or the internal VDD.
• Each conversion takes about 2 ms to complete.

92
The AD7302 D/A Converter (2 of 2)
- The output from either DAC is given by VOUTA/B
2 VREF (N/256) where, N is the digital
value to be converted.
93
Using the AD7302 to Generate Sawtooth Waveform

• Configure PB7PB0, PJ0PJ1 for output.
• Output the digital value from 0 to 255 and
  repeat. For each value, pull the PJ0 to low and
  then to high so that the value on pins PB7..PB0
  can be transferred to the AD7302.
• Pull the signal PJ1 to low during the process.

94
Example 7.10 Write a program to generate a
sawtooth waveform from VOUTA pin. The assembly
program is as follows include
"c\miniide\hcs12.inc" org 1500 movb FF,DDRB
configure PORTB for output bset DDRJ,03
configure PJ1PJ0 for output bclr PTJ,02
select VOUTA output loop inc PORTB increase the
output by one step bclr PTJ,01 generate a
rising edge on PJ0 pin bset PTJ,01
" bset PTJ,01 add 9 more bset
instructions to provide 2 ms bset PTJ,01 for
D/A conversion to complete bset PTJ,01
" bset PTJ,01 bset PTJ,01 bset PTJ
,01 " bset PTJ,01 bset PTJ,01 bse
t PTJ,01 bra loop to complete the D/A
conversion end The C language version of the
program is on next page.
95
include c\egnu091\include\hcs12.h void
main(void) DDRB 0xFF / configure PORTB
for output / DDRJ 0x03 / configure pins
PJ1PJ0 for output / PTJ 0xFD / pull
the signal A/B to low too select channel A
/ while (1) PTB 1 PTJ 0xFE
/ generate a rising edge / PTJ
0x01 / / PTJ 0x01 / use dummy
statements to provide 2 ms / PTJ 0x01 /
time for D/A conversion to complete / PTJ
0x01 PTJ 0x01 PTJ 0x01 PTJ
0x01 PTJ 0x01 PTJ
0x01 PTJ 0x01
96
Stepper Motor Control (1 of 7)

• It is digital in nature and provides high degree
  of control.
• In its simplest form, a stepper motor has a
  permanent magnet rotor and a stator consisting of
  two coils. The rotor aligns with the stator coil
  that is energized.
• By changing the coil that is energized, the rotor
  is turned.
• Figure 7.45a to 7.45d illustrate how the rotor
  rotates clockwise in full step.
• By changing the energizing order as shown in
  Figure 7.46, the stepper will rotate
  counterclockwise in full step.

97
Stepper Motor Control (2 of 7)
98
Stepper Motor Control (3 of 7)
99
Stepper Motor Control (4 of 7)
100
Stepper Motor Control (5 of 7)

• In a four-pole stepper motor shown in Figure 7.45
  7.46, a full step is 90 degrees.
• The stepper motor may also operate with half
  step. A half step occurs when the rotor (in a
  four-pole step) is moved to eight discrete
  positions (45º).
• To operate the stepper motor in half steps,
  sometimes both coils may have to be on at the
  same time. When two coils in close proximity are
  energized, there is a resultant magnetic field
  whose center will depend on the relative
  strengths of the two magnetic fields.
• Figure 7.47 illustrates the half-stepping
  sequence.
• The step sizes of the stepper motors may vary
  from approximately 0.72º to 90º. The most common
  step sizes are 1.8º, 7.5º, and 15º.
• The actual stator of a real motor has more
  segments than previously indicated. One example
  is shown in Figure 7.48.

101
Stepper Motor Control (6 of 7)
102
Stepper Motor Control (7 of 7)
103
Stepper Motor Drivers (1 of 6)

• Driving a step motor involves applying a series
  of voltages to the coils of the motor.
• A subset of coils is energized at a time to cause
  the motor to rotate one step. The pattern of
  coils energized must be followed exactly for the
  motor to work correctly.
• A microcontroller can easily time the duration
  that the coil is energized, and control the speed
  of the stepper motor in a precise manner.
• The circuit in Figure 7.49 shows how the
  transistors are used to switch the current to
  each of the four coils of the stepper motor.
• The diodes in Figure 7.49 are called fly back
  diodes and are used to protect the transistors
  from reverse bias.
• The transistor loads are the windings in the
  stepper motor. The windings are inductors,
  storing energy in a magnetic field.
• When the current is cut off, the inductor
  dispenses its stored energy in the form of an
  electric current.
• This current attempts to flow through the
  transistor, reversely biasing its
  collector-emitter pair. The diodes are placed to
  prevent this current from going through the
  transistors.

104
Stepper Motor Drivers (2 of 6)
105
Stepper Motor Drivers (3 of 6)

• The normal full-step sequence shown in Table 7.17
  should be used for high-torque applications.
• For lower-torque applications the half-step mode
  is used and its sequence is shown in Table 7.18.
• The microcontroller outputs the voltage pattern
  in the sequence shown in Table 7.17 or 7.18.
• Table 7.17 7.18 are circular. The values may be
  output in the order as shown in the table, which
  will rotate the motor clockwise or in the
  reverse order, which will rotate the motor
  counterclockwise.
• A delay of about 5 to 15 ms is required between
  two steps to prevent motor from missing steps.

106
Stepper Motor Drivers (4 of 6)
107
Stepper Motor Drivers (5 of 6)

• Example 7.11 Assuming that pins PP3...PP0 are
  used to drive the four transistor in Figure 7.30,
  write a subroutine to rotate the stepper motor
  clockwise one cycle using the half-step sequence.
• Solution

include "c\miniide\hcs12.inc" step1 equ 0A st
ep2 equ 08 step3 equ 09 step4 equ 01 step5 equ
05 step6 equ 04 step7 equ 06 step8 equ 02 half
_step movb FF,DDRP configure PTP for
output movb step1,PTP bsr delay10ms movb ste
p2,PTP bsr delay10ms movb step3,PTP bsr delay1
0ms movb step4,PTP
108
Stepper Motor Drivers (6 of 6)
movb step5,PTP bsr delay10ms movb step6,PTP
bsr delay10ms movb step7,PTP bsr delay10ms
movb step8,PTP bsr delay10ms movb step1,PTP b
sr delay10ms rts the following subroutine
waits for 10 ms delay10ms movb 90,TSCR1
enable TCNT fast flags clear movb 06,TSCR2
configure prescale factor to
64 bset TIOS,IOS0 enable OC0 ldd
TCNT addd 3750 start an output compare
operation std TC0 with 10 ms time
delay10ms wait_lp2 brclr TFLG1,01,wait_lp2 rts
end
109
Key Wakeups

• Many embedded products are powered by battery. To
  lengthen the battery life, most microcontrollers
  have incorporated power-saving modes such as the
  WAIT, STOP modes.
• All HCS12 members have incorporated the key
  wakeup feature which would wake up the CPU when
  keys connected to certain input ports are
  pressed.
• After entering the wait or stop mode, the MCU
  will be interrupted when one of these pins is
  pressed.
• The port H, J, and P of the HCS12 have
  implemented the key-wakeup function.
• The user selects the active edge for wakeup by
  programming the port device enable register and
  the port polarity select register.
• The port interrupt enable register and the
  interrupt flag register together allow the user
  to wake up the MCU.

110
Key Wakeup Initialization

• Step 1
• Set the direction of the key wakeup bits to input
  by writing zeros to the data direction register.
• Step 2
• Select the rising edge or the falling edge of the
  wake up pin to interrupt the MCU by programming
  the related registers.
• Step 4
• Write the service routine for the key wakeup
  interrupt and initialize the key wakeup interrupt
  vector.
• Step 5
• Clear any flags that have been set in the key
  wakeup flag register.
• Step 6
• Enable the key wakeup function by setting the
  appropriate bits in the wakeup interrupt enable
  register.
• Step 7
• Clear the global interrupt mask (the I bit of the
  CCR register).

111
Considerations of the Key Wakeup Application

• Many applications are designed to be a wait loop
  that waits for the user to request for service.
• When a request is entered, the application calls
  an appropriate routine to provide the service.
  After the service is done, the routine returns to
  the wait loop.
• After the completion of a service to a user
  request, the application software starts a timer.
  
• If the user enters another command before the
  timer times out, the application software resets
  the timer and responds to the user request.
• If the timer times out before the user makes
  another service request, the application software
  puts the microcontroller in low power mode to
  save power.
• Whenever the user presses a key, an interrupt is
  generated to wake up the microcontroller.
• The service routine for the key interrupt simply
  clears the key wakeup flag and returns to the
  wait loop.
• Since we can choose either the rising or the
  falling edge to interrupt the CPU, the choice is
  based on whether there is pull-down or pull-up
  device inside the chip.
• If the MCU has internal pull down device, then
  choose the rising edge as the active edge.
  Otherwise, choose the falling edge as the active
  edge.

112
(No Transcript)
113

• Example 7.13 Write an instruction sequence to
  configure Port P upper four pins for wakeup
  feature. Program the Port P so that pins
  PP7...PP4 generate interrupt whenever there is a
  falling edge applied to any one of these four
  pins.
• Solution

include c\miniide\hcs12.inc bclr DDRP,F0
configure PPlt74gt pins for input bset PERP,F
0 enable PP7PP4 pins pull device bclr PPSP,F
0 choose pull-up device movb FF,PIFP clear
the Port P key wakeup flags bset PIEP,F0
enable Port P interrupt cli enable key wakeup
interrupt globally