CSE%2091%20Fall%202009%20Embedded%20Systems

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CSE 91 Fall 2009Embedded Systems

• Rajesh K. Gupta
• Computer Science and Engineering
• University of California, San Diego.

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Topics We Will Discuss

• What are embedded systems?
• How do computers interface?
• What has that got to do with computers and
  chips?
• Hands-on Exercise Do It Yourself Computing
• How do we connect different components?
• How do we program embedded systems?

Keywords Embedded Computer Programmable
Systems Systems on Chip PSOC I2C, Serial, USB,
ASCII ISA
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"Embedded Everywhere"
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The Computing Experience

• The Computer Center
• Mainframe computing
• The Personal Computer
• Desktop, laptop, palm top computing
• The Ubiquitous Embedded Computer
• Mobile, purpose-built.

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Hardware Architecture Organization

• Computer Architecture is how a builder/user sees
  it
• How do you see your house? This building?
• Instruction Set Architecture (ISA), Memory System
  Architecture
• Computer Organization refers to the structure of
  a computer

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Software Architecture
Embedded Software And Configuration
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A Personal Computer (PC)

• Uses commodity components and standard interfaces
  to build the machine
• Choose different components for performance,
  capacity, cost
• Faster hard drive, processor, memory, interfaces

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PC Components

• Case
• desktop, minitower, mid case, mid tower, full
  tower, large tower
• include a power supply (typically 200 watts)
• CPU and CPU fan
• sold as a chip
• Motherboard
• single-board computer
• contains place holders for CPU and Memories
• Memory modules
• Interfaces
• Video (card and monitor)
• Others (I/O card) Floppy, CD-ROM, Keyboard,
  Hard drive, Sound card, Speakers, Modem, Tape/zip
  , Mouse

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168-pin SDRAM
The Stuff at Frys
184-pin DDR-SDRAM
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Not at Frys Yet!
Mani Srivastava, UCLA
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Personal Computing

• Low cost and general purpose

CPU
DATA
INST
BUS
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Computer Organization
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3
2
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Drives Input devices Output devices Networking
Interface
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Memory
2-3 GHz
50 ns SIMM PC2-5300 667 MHz DIMM
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CPU Memory Interaction
Clock
200 ns
CPU
Memory
Address
clock
R/W
addr
VALID
Data
500 ns

• CPU controlled by a clock pulse.
• Memory is controlled by R/W control signals.
• CPU must synchronize its memory read, write
  operations with respect to its internal clock.
• Example 5 MHz clock, 500 ns access time.

R/W
VALID
data
WRITE CYCLE
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A Processors Interfaces

• Two basic types
• Communicate via memory
• Sender writes to a memory location
• Receiver reads from that memory location
• Communicate directly
• Sender and receivers connected by ports
• How do we measure goodness of an interface?
• Maximum data-rate of transfer? Bits or bytes per
  second?

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What is this connector?
A Serial Port
9-pin RS232C DE-9
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Then What Are These?
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From RS232c to USB

• D-Sub connectors
• A 15 pin
• B 25 pin
• C 37 pin
• D 50 pin
• E 9 pin
• RS232 was DB25
• RS232c was DE9
• Specified by EIA in 1969
• Electricals (voltage levels)
• Signaling rate, timing, slew-rate
• Mechanicals
• But not character encoding, character framing,
  protocols

Question 1 How many keys on your
keyboard? Question 2 How many bits it will take
to encode these?
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What is ASCII?

• American Standard Code for Information
  Interchange
• Published in 1963, revised 1967, 1986
• 128 characters, incl. 33 non-printing or control
• 94 printable characters 26 10 11-25 symbols
• Is SPACE printable?
• 8-bit extension by MAC OS Roman
• Unicode and Universal Character Set (UCS)
• UTF-8, UTF-16, UTF-32

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(No Transcript)
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Interface Basics

• Who/Where to send/receive information?
• Ports mechanicals, electrical
• What information to send?
• Signals and Packets Electrical signaling,
  logical encoding
• How to send the information?
• Protocols synchronous, asynchronous

How do we measure goodness of an interface?
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1. Ports

• Which door to knock at or open?
• All processors already have one door memory
• Memory-mapped IO
• They may have additional I/O ports
• How are these ports identified?
• How are devices connecting to these ports
  identified?
• Mechanically, Electrically, or at a higher
  level
• Memory-mapped versus dedicated IO
• What happens to CPU when I/O operation is in
  progress?

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2. Signaling

• How many wires? What do they carry?
• Serial signaling Send one bit at a time
• Direction of signaling Half and Full Duplex
• Synchronous versus Asynchronous
• Asynchronous serial communication
• Send a START signal prior to each byte
• And a STOP signal after each byte
• Generally use more than 8-bit to transmit a byte
  (10 to 12)
• UART Universal Asynchronous Receiver Transmitter
• Again, no shared clock. The RX must lock onto
  data and detect individual bits
• TX is a Parallel-to-Series converter
• RX is a Series-to-Parallel converter

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3. Protocols

• Request/Acknowledge Handshakes
• RTS Request to Send Transmitter (TX) asserts
  RTS
• CTS Clear to Send Receiver (RX) asserts CTS
• This gives you flow control
• i.e., data transfer can proceed at a rate that is
  acceptable
• Let us examine two protocols
• I2C and USB

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I2C inter-integrated circuit

• Two-wire
• A microcontroller can control a network of
  devices with just two general-purpose IO pins and
  software. (upto a few meters)
• Connects multiple devices on a multi-drop bus
• Devices can be attached or detached without
  affecting other devices
• 7-bit address space, 16 reserved, 112 nodes
  maximum
• 10 kbps (low), 100 kbps, 400 kbps (fast), FM 1
  Mbps, HS 3.4 Mbps

• 2008 R. Gupta, UCSD

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I2C Wires

• Two bidirectional wires
• SDA Serial Data
• SCL Serial Clock
• Open drain normally high when not in use
• MASTER node issues the SCL and addresses SLAVES
• SLAVE node receives the SCL and the address
• Wired AND logical function.

• 2008 R. Gupta, UCSD

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So, how do we write or read?

• Normally, both SDA and SCL are high
• sense before you drive a line
• A device that wants to write pulls SDA low
• Followed by SCL going low
• So, everyone else knows that a transmission is
  starting

• 2008 R. Gupta, UCSD

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START, Data, Data,,Data, STOP!
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Putting it together

• Start Condition With SCL low, SDA goes H?L
• Bits are sampled on the rising edge of SCL
• Stop Condition With SCL high, SDA goes L?H

• 2008 R. Gupta, UCSD

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I2C Protocol

• Any number of bytes in an I2C packet
• MSB first, each bytes transmitted must be
  acknowledged by the receiver
• After each 8th bit, MASTER releases SDA and then
  generates an additional clock pulse on SCL
• Receiver can then acknowledge by pulling SDA low
• Receiver can always abort the transmission by
  holding SCL low
• Can not go up by the MASTER, thus no bit sampling
  edge

• 2008 R. Gupta, UCSD

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Bi-directional Data Transfers
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I2C Protocol Actions

• Master sends START
• followed by 7-bit address of the Slave
• followed by single bit representing write to (0)
  or read from (1) the slave.
• Slave responds with ACK bit for that address
• Master then continues in either TX or RX mode
• Communication transfer follows.
• All other MASTERS monitor START and STOP bits.

• 2008 R. Gupta, UCSD

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Note the direction of signaling
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Standardizing the Standard USB

• RS232C was not standard enough
• Too much flexibility (on data rate, parity, flow
  control)
• USB standardized the door and the lane
• Software takes care of the data, information side
• The OS is aware of the device interface
• Up to 127 devices. One standard cable.
• Devices identify themselves. Not the interface.
• USB 1.1 12 Mbps (Normal), 1.5 Mbps (Low)
• USB 2.0 480 Mbps (High)
• USB 3.0 4.8 Gbps (Super)

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USB
1 Vbus USB device power (5 V) Red
3 D Differential data line Green
2 D- Differential data line White
4 GND Power and signal ground Black

• Shielded 4-wire cable
• One host in a network host controller
• Upstream versus downstream connection and
  connectors (A versus B)
• Host controller either directly connects to
  device (star) or through a hub (tiered star)
• Because of the connectors, no device-to-device
  connections
• When a device is attached to the network
• Based on its identification, the host OS
  determines the software driver to be used,
• device is assigned a unique address and
• host requests its internal configuration.

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Classes of Devices

• Host controller know about the following class of
  devices
• Audio
• HID
• Hub
• IrDA
• Mass storage HD, CDROM, DVD
• Monitor
• Communications
• Physical interface device
• Power
• Printer
• Imaging
• Common class

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USB Packets

• All data transfers under the control of the host
  controller
• Four type of data transfers
• Control transfer configure the bus and devices
  on the bus
• Bulk transfer move data asynchronously
• Isochronous transfer move time-critical data
  (e.g, audio)
• Interrupt transfer retrieve data at regular
  intervals
• A packet contains
• SYNC byte, Packet ID, Content, CRC
• Four type of packets
• Token, data, handshake, preamble
• Defined processes for how a device is recognized,
  joins the network and how it communicates with
  the host controller.

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Embedding Clock

• Recover clock from data
• Manchester Encoding
• Each data bit (1 or a 0) has at least one
  transition
• So, we can recover clock from data

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The Chip A Packaged Part
Quad Flat Pack (QFP)
Ball Grid Array (BGA)
http//education.netpack-europe.org/chipp.php
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CypressPSoC
I/O Pins(Each port up to 8 bits)
8-Bit CPU CoreWith RAM and ROM
Blocks for processingDigital signals
Blocks for processingAnalog signals
All Toys such as ADCs, Timers, RS232, etc.
are madeout of configurable digital andanalog
blocks
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What can you do with Digital/Analog Blocks?

• Analog-to-Digital Converters
• 8- to 14-bit resolution, multiple configurations
• Digital-to-Analog Converters
• 6- to 9-bit resolution
• Timers, Counters, PWMs
• 8- to 32-bit resolution
• Serial Interfaces
• RS232, I2C, SPI
• Programmable Gain Amplifiers, Filters
• Random sequences
• Etc.

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PSoC 29x66 Mechanical Characteristics
28 Pin 3 I/O Ports
44 Pin 5 I/O Ports
48 Pin 6 I/O Ports
29x66-Series PSoCs come infive sizes.The
primary difference is the number of I/O pins.

• PDIP Plastic Dual Inline Package
• SSOP Shrink Small Outline Package
• SOIC Small Outline Integrated Circuit
• TQFP Thin Quad Flat Pack
• QFN Quad Flat No Leads

100 Pin 8 I/O Ports
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Key PSoC Electrical Characteristics

• Supply voltage either 3.3V or 5.0V
• Built in controller (SMP) provides 3.3V from a
  single 1.5V battery or 5.0V from two 1.5V
  batteries
• Clock speed 930 KHz 24 MHz
• Can use internal oscillator or external crystal
• Power usage (running) 15 70 mW
• AA battery supplies about 2 Watt-Hours
• Around 80 hours of life on one AA
• Power usage (sleep) 10 70 uW
• Around 80,000 hours or 10 years of life on one AA

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The PSoC CPU Core M8C
System Bus 8 Bits WidePasses data between the
CPU, memory, ports and peripherals
Flash Memory 32K Bytes in 29x66Holds program
code (nonvolatile!)Can be used to hold user data.
Supervisory ROMHolds boot-up code andcode to
read from flash memory.
SRAM 2048 Bytes in 29x66Regular memory for use
of CPUand peripherals. 256 bytes
easilyaccessible remainder requires paging.
Interrupt ControllerAllows external events to be
communicated to the CPU
M8C CPU CoreExecutes instructions
(arithmetic,logic, data movement,
control)Modifies registers and memory
Clock Sources 930KHz 24MHzProvides basic
timing for the CPUand peripheral devices.
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Hands-on Exercise

• Tasks
• Design the machine
• Actually, a circuit that connects an LED to a
  control SWITCH
• You build the machine in a schematics editor
  (PSOC Designer)
• Program the machine
• Write the C-code for the program that will run on
  the machine.
• Build the machine
• Wire-wrap the connections
• Download the configuration and embedded code.

VLSI/CAD, Computer Architecture
Software, Programming, OS
Prototyping
In Embedded Systems we do it all, for a given
purpose Purpose Built Machines!
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Design the machine Find Components and Connect
in Editor
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Program the machine

• How do you make sure that the program never dies?
• Repeat forever
• How do you sample the switch?
• Read PORT as a collection of 8-bits
• Extract the bit you want through a mask
• How do you turn ON, OFF the LED?
• Make calls to LED routines (written in assembly
  why?)

Where is the Operating System? Where does the
code reside?
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Build the machine
What is a HOST computer? What happens to the
programmer after the machine is built?