Hierarchical Memory Systems Cache memory

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Hierarchical Memory SystemsCache memory
Chapter 9

• Prof. Sin-Min Lee
• Department of Computer Science

CS147 Lecture 18
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The connection between the CPU and cache is very
fast the connection between the CPU and memory
is slower
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Cache

• The lowest level of the hierarchy is a small,
  high speed memory called cache.
• It greatly improves CPU performance.
• It is implemented with Static RAM chips and it
  runs at about 5 to 10 ns.
• There are two types of cache memory
• A primary cache is located on the CPU chip, it is
  small because it competes for space on the CPU
  chip.

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The performance of a memory system is defined by
two different measures, the access time and the
cycle time. Access time, also known as response
time or latency, refers to how quickly the memory
can respond to a read or write request. Several
factors contribute to the access time of a memory
system. The main factor is the physical
organization of the memory chips used in the
system. This time varies from about 80 ns in the
chips used in personal computers to 10 ns or less
for chips used in caches and buffers (small, fast
memories used for temporary storage, described in
more detail below).
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The performance of a hierarchical memory is
defined by the effective access time, which is a
function of the hit ratio and the relative access
times between successive levels of the hierarchy.
For example, suppose the cache access time is
10ns, main memory access time is 100ns, and the
cache hit rate is 98. Then the average time for
the processor to access an item in memory is
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• Assume each memory block can only go in one
  specific cache block
• This is called a Direct Mapped organization.
• The location of the memory block in the cache
  (i.e., the block number in the cache) is the
  memory block number modulo the number of blocks
  in the cache.
• For example, if the cache contains 100 blocks,
  then memory block 34452 is stored in cache block
  52. Memory block 352 is also stored in cache
  block 52 (but not at the same time, of course).
• In real systems the number of blocks in the cache
  is a power of 2 so taking modulo is just
  extracting low order bits.
• Example if the cache has 16 blocks, the location
  of a block in the cache is the low order 4 bits
  of block number

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There are three methods in block placement
Direct mapped if each block has only one place
it can appear in the cache, the cache is said to
be direct mapped. The mapping is usually (Block
address) MOD (Number of blocks in cache) Fully
Associative if a block can be placed anywhere
in the cache, the cache is said to be fully
associative. Set associative if a block can
be placed in a restricted set of places in the
cache, the cache is said to be set associative .
A set is a group of blocks in the cache. A block
is first mapped onto a set, and then the block
can be placed anywhere within that set. The set
is usually chosen by bit selection that is,
(Block address) MOD (Number of sets in cache)
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Cache (cont.)
Bits 2-4 of main memory address is the cache
address (index). The upper 5 bits of main memory
(tag) is stored in cache along with data. If tag
and index requested from CPU matches, its a
cache hit.

• Direct Mapping Cache

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•                                                   
                                           

• A pictorial example for a cache with only 4
  blocks and a memory with only 16 blocks.

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