Chapter 2 Instruction Sets

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Chapter 2 Instruction Sets

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Title: Chapter 2 Instruction Sets

1
Chapter 2Instruction Sets

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(Slides are taken from the textbook slides)

2
Outline

Computer Architecture Introduction
ARM Processor
SHARC Processor

3
von Neumann Architecture

Memory holds data and instructions
CPU fetches instructions from memory
Separate CPU and memory distinguishes
programmable computer
CPU registers help out program counter (PC),
instruction register (IR), general-purpose
registers, etc.

4
Von Neumann Architecture
memory
address
CPU
PC
200
data
IR
ADD r5,r1,r3
ADD r5,r1,r3
200
5
Harvard Architecture (NOT von Neumann
Architecture)
address
CPU
data memory
PC
data
address
program memory
data
6
von Neumann vs. Harvard

Harvard cant use self-modifying code
Harvard allows two simultaneous memory fetches
Most DSPs use Harvard architecture for streaming
data
greater memory bandwidth
more predictable bandwidth

7
RISC vs. CISC

Complex instruction set computer (CISC)
many addressing modes
many operations
Reduced instruction set computer (RISC)
load/store
pipelinable instructions

8
Instruction Set Characteristics

Fixed vs. variable length
Addressing modes
Number of operands
Types of operands

9
Programming model

Programming model registers visible to the
programmer.
Some registers are not visible (IR).

10
Multiple implementations

Successful architectures have several
implementations
varying clock speeds
different bus widths
different cache sizes
etc.

11
Assembly language

One-to-one with instructions (more or less).
Basic features
One instruction per line.
Labels provide names for addresses (usually in
first column).
Instructions often start in later columns.
Columns run to end of line.

12
ARM Assembly Language Example

label1 ADR r4,c
LDR r0,r4 a comment
ADR r4,d
LDR r1,r4
SUB r0,r0,r1 comment

13
Pseudo-ops

Some assembler directives dont correspond
directly to instructions
Define current address.
Reserve storage.
Constants.
Examples
In ARM
BIGBLOCK 10 allocate a block of 10-bytes
memory and initialize to 0
In SHARC
.global BIGBLOCK
.var BIGBLOCK10 0, 0, 0, 0, 0, 0, 0, 0, 0, 0

14
Outline

Computer Architecture Introduction
ARM Processor
ARM assembly language
ARM programming model
ARM memory organization
ARM data operations
ARM flow of control
SHARC Processor

15
ARM Versions

ARM architecture has been extended over several
versions
We will concentrate on ARM7
ARM7 is a von Neumann architecture
ARM9 is a Harvard architecture

16
ARM assembly language

Fairly standard assembly language
LDR r0,r8 a comment
label ADD r4,r0,r1

17
ARM programming model

16 general-purpose registers (including PC)
One status register

r0
r8
r1
r9
0
31
r2
r10
CPSR
r3
r11
r4
r12
r5
r13
r6
r14
r7
r15 (PC)
18
Endianness

Relationship between bit and byte/word ordering
defines endianness

MSB
LSB
word 4
byte 3
byte 2
byte 1
byte 0
word 0
little-endian
MSB
LSB
word 4
byte 0
byte 1
byte 2
byte 3
word 0
big-endian
19
ARM data types

Word is 32 bits long
Word can be divided into four 8-bit bytes
ARM addresses can be 32 bits long
Address refers to byte
Address 4 starts at byte 4
Can be configured at power-up as either little-
or bit-endian mode

20
ARM status bits

Every arithmetic, logical, or shifting operation
sets CPSR bits
N (negative), Z (zero), C (carry), V (overflow).
Examples
-1 1 0
0xffffffff 0x1 0x0 ? NZCV 0110
231-11 -231
0x7fffffff 0x1 0x80000000 ? NZCV 0101

21
ARM data instructions

Basic format
ADD r0,r1,r2
Computes r1r2, stores in r0
Immediate operand
ADD r0,r1,2
Computes r12, stores in r0

22
ARM data instructions

ADD, ADC add (w. carry)
SUB, SBC subtract (w. carry)
RSB, RSC reverse subtract (w. carry)
MUL, MLA multiply (and accumulate)

AND, ORR, EOR
BIC bit clear
LSL, LSR logical shift left/right
ASL, ASR arithmetic shift left/right
ROR rotate right
RRX rotate right extended with C

23
Data operation varieties

Logical shift
fills with zeroes
Arithmetic shift
fills with sign bit on shift right
RRX performs 33-bit rotate, including C bit from
CPSR above sign bit.

24
ARM comparison instructions

CMP compare
CMN negated compare
TST bit-wise test (AND)
TEQ bit-wise negated test (XOR)
These instructions set only the NZCV bits of CPSR.

25
ARM move instructions

MOV, MVN move (negated)
MOV r0, r1 sets r0 to r1

26
ARM load/store instructions

LDR, LDRH, LDRB load (half-word, byte)
STR, STRH, STRB store (half-word, byte)
Addressing modes
register indirect LDR r0,r1
with second register LDR r0,r1,-r2
with constant LDR r0,r1,4
Cannot refer to address directly in an
instruction
Generate value by performing arithmetic on PC
(r15)
ADR pseudo-op generates instruction required to
calculate address
ADR r1,FOO

27
Example C assignments

C
x (a b) - c
Assembler
ADR r4,a get address for a
LDR r0,r4 get value of a
ADR r4,b get address for b, reusing r4
LDR r1,r4 get value of b
ADD r3,r0,r1 compute ab
ADR r4,c get address for c
LDR r2,r4 get value of c
SUB r3,r3,r2 complete computation of x
ADR r4,x get address for x
STR r3r4 store value of x

28
Example C assignment

C
y a(bc)
Assembler
ADR r4,b get address for b
LDR r0,r4 get value of b
ADR r4,c get address for c
LDR r1,r4 get value of c
ADD r2,r0,r1 compute partial result
ADR r4,a get address for a
LDR r0,r4 get value of a
MUL r2,r2,r0 compute final value for y
ADR r4,y get address for y
STR r2,r4 store y
Register reuse

29
Example C assignment

C
z (a ltlt 2) (b 15)
Assembler (register reuse)
ADR r4,a get address for a
LDR r0,r4 get value of a
MOV r0,r0,LSL 2 perform shift
ADR r4,b get address for b
LDR r1,r4 get value of b
AND r1,r1,15 perform AND
ORR r1,r0,r1 perform OR
ADR r4,z get address for z
STR r1,r4 store value for z

30
Additional addressing modes

Base-plus-offset addressing
LDR r0,r1,16
Loads from location r116
Auto-indexing increments base register
LDR r0,r1,16!
Adds 16 to r1, then use new value as address
Post-indexing fetches, then does offset
LDR r0,r1,16
Loads r0 from r1, then adds 16 to r1.

31
ARM flow of control

Branch operation
B 100
PC-relative add 400 to PC
Can be performed conditionally.
All operations can be performed conditionally,
testing CPSR
EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT,
GT, LE

32
Example if statement

C
if (a gt b) x 5 y c d else x c - d
Assembler
compute and test condition
ADR r4,a get address for a
LDR r0,r4 get value of a
ADR r4,b get address for b
LDR r1,r4 get value for b
CMP r0,r1 compare a lt b
BGE fblock if a gt b, branch to false block
true block
MOV r0,5 generate value for x
ADR r4,x get address for x
STR r0,r4 store x
ADR r4,c get address for c

33
If statement, contd

LDR r0,r4 get value of c
ADR r4,d get address for d
LDR r1,r4 get value of d
ADD r0,r0,r1 compute y
ADR r4,y get address for y
STR r0,r4 store y
B after branch around false block
false block
fblock ADR r4,c get address for c
LDR r0,r4 get value of c
ADR r4,d get address for d
LDR r1,r4 get value for d
SUB r0,r0,r1 compute a-b
ADR r4,x get address for x
STR r0,r4 store value of x
after ...

34
Example conditional execution

Use predicates to control which instructions are
executed
true block, condition codes updated only by CMP
no need for BGE fblock and B after
MOVLT r0,5 generate value for x
ADRLT r4,x get address for x
STRLT r0,r4 store x
ADRLT r4,c get address for c
LDRLT r0,r4 get value of c
ADRLT r4,d get address for d
LDRLT r1,r4 get value of d
ADDLT r0,r0,r1 compute y
ADRLT r4,y get address for y
STRLT r0,r4 store y

35
Conditional execution, contd

false block
ADRGE r4,c get address for c
LDRGE r0,r4 get value of c
ADRGE r4,d get address for d
LDRGE r1,r4 get value for d
SUBGE r0,r0,r1 compute a-b
ADRGE r4,x get address for x
STRGE r0,r4 store value of x
Conditional execution works best for small
conditionals

36
Example switch statement

C
switch (test) case 0 break case 1
Assembler
ADR r2,test get address for test
LDR r0,r2 load value for test
ADR r1,switchtab load address for switch table
LDR r15,r1,r0,LSL 2 index switch table
switchtab DCD case0
DCD case1
...
LDR
Shift r0 2 bits to get word address
Load content of Mr0r1 to r15 (PC)

37
Example FIR filter

C for finite impulse response (FIR) filter
for (i0, f0 iltN i)
f f cixi / xi periodic samples /
Assembler
loop initiation code
MOV r0,0 use r0 for I
MOV r8,0 use separate index for arrays
ADR r2,N get address for N
LDR r1,r2 get value of N
MOV r2,0 use r2 for f
ADR r3,c load r3 with base of c
ADR r5,x load r5 with base of x

38
FIR filter, contd

loop body
loop LDR r4,r3,r8 get ci
LDR r6,r5,r8 get xi
MUL r4,r4,r6 compute cixi
ADD r2,r2,r4 add into running sum
ADD r8,r8,4 add 1 word offset to array index
ADD r0,r0,1 add 1 to i
CMP r0,r1 exit?
BLT loop if i lt N, continue

39
ARM subroutine linkage

Branch and link instruction
BL foo
Copies current PC to r14.
To return from subroutine
MOV r15,r14

40
Nested subroutine calls

Nesting/recursion requires coding convention
C
void f1(int a) f2(a)
Assembly
f1 LDR r0,r13 load arg into r0 from stack
r13 is stack pointer
call f2()
STR r13!,r14 store f1s return adrs
STR r13!,r0 store arg to f2 on stack
BL f2 branch and link to f2
return from f1()
SUB r13,4 pop f2s arg off stack
LDR r13!,r15 restore reg and return

41
Summary of ARM

Load/store architecture
Most instructions are RISC, operate in single
cycle
Some multi-register operations take longer
All instructions can be executed conditionally
Details please refer to Chapter 2 of the textbook

42
Outline

Computer Architecture Introduction
ARM Processor
SHARC Processor
SHARC programming model
SHARC assembly language
SHARC memory organization
SHARC data operations
SHARC flow of control

43
SHARC programming model

Register files
R0-R15 (aliased as F0-F15 for floating point)
Status registers.
ASTAT arithmetic status.
STKY sticky.
MODE 1 mode 1.
Loop registers.
Data address generator registers.
Interrupt registers.

44
SHARC assembly language

Algebraic notation terminated by semicolon
R1DM(M0,I0), R2PM(M8,I8) ! comment
label R3R1R2

45
SHARC data types

32-bit IEEE single-precision floating-point.
40-bit IEEE extended-precision floating-point.
32-bit integers.
Memory organized internally as 32-bit words with
a 32-bit address.
An instruction is 48 bits.
Floating-point can be
rounded toward zero or nearest.
ALU supports saturation arithmetic (ALUSAT bit in
MODE1).
Overflow results in max value, not rollover.

46
SHARC microarchitecture

Modified Harvard architecture.
Program memory can be used to store some data.
Register file connects to
multiplier
shifter
ALU.

47
Multiplier

Fixed-point operations can accumulate into local
MR registers or be written to register file.
Fixed-point result is 80 bits.
Floating-point results always go to register
file.
Status bits negative, under/overflow, invalid,
fixed-point underflow, floating-point underflow,
floating-point invalid.

48
ALU/shifter status flags

ALU
zero, overflow, negative, fixed-point carry,
inputsign, floating-point invalid, last op was
floating-point, compare accumulation registers,
floating-point under/overflow, fixed-point
overflow, floating-point invalid
Shifter
zero, overflow, sign

49
Flag operations

All ALU operations set AZ (zero), AN (negative),
AV (overflow), AC (fixed-point carry), AI
(floating-point invalid) bits in ASTAT.
STKY is sticky version of some ASTAT bits.

50
Example data operations