Operand Addressing and Instruction Representation

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Operand Addressing and Instruction Representation

• Chapter 6

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0, 1, 2, or 3 Address Designs

• Many processors do not allow an arbitrary number
  of operands because
• 1) Variable length instructions require more
  fetching and decoding, which is inefficient
  compared to fixed length ones.
• 2) Fetching an arbitrary number of operands
  takes time, causing the processor to run slower.

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Zero Operands Per Instruction

• Also known as a stack architecture
• Operands must be implicit
• Operands are fetched from the top of the stack
  and the result is placed back on the stack.

• Ex To add 7 to a variable X
• push X
• push 7
• add
• pop X

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One Operand per Instruction

• Relies on an implicit operand the accumulator
• The accumulators value is extracted, manipulated
  and restored.
• Ex
• add X
• Is applied as
• accumulator lt- accumulator X

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1-Address Design Limitations

• Works well for arithmetic and logical operations
  but can not copy memory easily.
• Requires loading memory into the accumulator and
  restoring it elsewhere.
• Especially slow at moving graphics objects in
  display memory.

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2-Address Architecture

• Overcomes limitations of 1-address architectures
• Operations can be applied to a specified value
  instead of the accumulator

• To move memory
• move Q, R
• Copies data from Q to R
• To add
• add X, Y
• Adds X and Y and stores the sum in Y
• Y lt- X Y

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3-Address Design

• Not necessary but useful for processors with
  multiple general-purpose registers
• Third operand is used as a destination

• Ex
• add X, Y, Z
• Adds X and Y and stores the sum in Z
• Z lt- X Y

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Operand Sources and Immediate Values

• Operands that specify a source can be
• 1) a signed constant
• 2) an unsigned constant
• 3) the contents of a register
• 4) the value in a memory location

• Operands that specify a destination can be
• 1) a single register
• 2) a pair of contiguous registers
• 3) a memory location

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The Von Neumann Bottleneck

• Conventional computers use the Von Neumann
  architecture which stores both programs and data
  in memory
• Instructions stored in memory means at least one
  memory reference is needed per instruction
• Operands specifying locations in memory require
  additional trips

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Explicit and Implicit Operand Encoding

• A string of bits is insufficient to represent an
  operand as an instruction.
• The processor needs to know what the bits
  represent
• There are two methods for specifying the
  interpretation of operands
• 1) Implicit operand encoding
• 2) Explicit operand encoding

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Implicit Operand Encoding

• The processor uses multiple opcodes for a given
  operation.
• Each opcode corresponds to a particular set of
  operands
• The list of opcodes may grow very large

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Example opcode operands meaning --------------
------------------------------------------------ A
dd register r1, r2 r1lt- r1r2 Add imm signed r1,
imm r1lt- r1imm Add imm unsigned r1, Uimm r1lt-
r1Uimm Add memory r1, mem r1lt- r1mem
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Explicit Operand Encoding

• Associates the type of information with each
  operand

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Operands That Combine Multiple Values

• Some processors can compute an operand value by
  extracting and combining values from multiple
  sources
• The register-offset approach requires each
  operand to specify a type, register, and offset
  from that register

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Register-offset Example

• The processor adds the contents of the offset
  field to the contents of the specified register
  to obtain a value that is then used as the
  operand
• Ex the first operand consists of the current
  contents of register 2 minus the constant 17

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Tradeoffs in The Choice of Operands

• There is no best operand design choice. Each has
  been used in practice.
• Each choice has a tradeoff between
• 1) ease of programming
• 2) size of the code
• 3) speed of processing
• 4) size of the hardware

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Ease of Programming

• Complex forms of operands make programming easier
• Allowing an operand to specify a register plus an
  offset makes data aggregate references
  straightforward
• A 3-address approach that provides an explicit
  target means the programmer does not have to
  write separate instructions to get the data to
  its final destination

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Fewer Instructions

• Allowing an operand to specify both a register
  and an offset results in fewer instructions.
• Increasing the number of addresses per
  instruction also lowers the number of
  instructions
• Fewer instructions makes each instruction larger

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Smaller Instructions

• Limiting the number of operands, the set of
  operand types, or the maximum size of an operand
  keeps instructions small.
• Some of the smallest and least powerful
  processors limit operands to registers (except
  for load and store operations)
• Increases the number of instructions needed

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Larger Range of Immediate Values

• The size of a field in the operand determines the
  numeric range of immediate vales
• Increasing the size allows larger values but
  results in larger instructions

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Faster Operand Fetch and Decode

• Limiting the number of operands and the possible
  types of each operand allows hardware to operate
  faster
• To maximize speed, avoid register-offset designs
  because hardware can fetch an operand from a
  register much faster than it can compute the
  value from a register plus an offset

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Decreased Hardware Size

• Decoding complex forms of operands requires more
  hardware in a limited space
• Limiting the types and complexity of operands
  reduces the size of the circuitry required
• Decreased instruction size means increased number
  of instructions and larger programs

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Values in Memory and Indirect Reference

• Processors include at least one instruction whose
  operand is interpreted as a memory address, which
  the processor fetches
• Memory lookup helps ease of programming but slows
  down performance
• Some processors extend memory references by
  permitting various forms of indirection

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Indirection Examples

• If an operand specifies indirection through
  register 6, the processor
• 1) Obtains the current value from register 6
• 2) interprets it as a memory address and fetches
  the operand from memory
• Indirection can be permitted through a memory
  address. The operand contains a memory address,
  M, and specifies indirect reference. The
  processor
• 1) Obtains the value in the operand itself
• 2) interprets it as a memory address and fetches
  the value from memory
• 3) uses that value as another memory address,
  and fetches the operand from memory

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Operand Addressing Modes

1. Immediate value
2. Direct register reference
3. Indirect through a register
4. Direct memory reference
5. Indirect memory reference