LCSL Logic Circuit Simulation Language

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LCSLLogic Circuit Simulation Language

• Bogdan Caprita
• Julian Maller
• Sachin Nene
• Chaue Shen

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Verilog

• Hardware design language (HDL)
• Introduced in 1985
• Main HDL along with VHDL
• Implement VLSI Circuits
• Design simulation

3
Fundamentals

• Based on Confluence language
• More abstraction
• Functional Language
• Writes comparable Verilog code

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Why use LCSL over Verilog?

• -Less verbose
• -Easier to understand
• -Recursion!

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Implementation

• Design circuit(s) in LCSL
• Use Verilog code for simulation, synthesis

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LCSL is simpler

• Xor lt- comp A B -X
• X lt- A '' B
• end
• Sys lt- Xor
• VectorInput, "In1" 1 4, Sys.A
• VectorInput, "In2" 2 4, Sys.B
• VectorOutput, "Out" 3 Sys.X
• Set, "BuildName" "Xor"

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Verilog Counterpart

• module OneBitXor (In1_i, In2_i, Out_o)
• input 30 In1_i
• input 30 In2_i
• output 30 Out_o
• wire 30 n1
• assign n1 In1_i In2_i
• assign Out_o n1
• endmodule

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Back to example

• Xor lt- comp A B -X
• X lt- A '' B
• end
• Sys lt- Xor
• VectorInput, "In1" 1 4, Sys.A
• VectorInput, "In2" 2 4, Sys.B
• VectorOutput, "Out" 3 Sys.X
• Set, "BuildName" "OneBitXor"

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Circuit implemented
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Functional Programming

• Lambda functions
• Beta reductions
• Variables
• Recursion
• Evaluation

?
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Another example

• Xor lt- comp A B -X
• X lt- A '' B
• end
• BusXor lt- comp A B -X
• if width A 0
• X lt- ''
• else
• Xor, 'lsb' A 'lsb' B,
  BitX
• BusXor, 'msbs' A 'msbs' B,
  SubX
• X lt- SubX '' BitX
• end
• end

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Another example (Contd)

• Sys lt- BusXor
• VectorInput, "In1" 1 4, Sys.A
• VectorInput, "In2" 2 4, Sys.B
• VectorOutput, "Out" 3 Sys.X
• Set, "BuildName" "NBitXor"

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Circuit implemented
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And the Verilog for it

• module NBitXor (In1_i, In2_i, Out_o)
• input 30 In1_i
• input 30 In2_i
• output 30 Out_o
• wire 30 n1
• NBitXor_1 s1 (In1_i, In2_i, n1)
• assign Out_o n1
• endmodule
• module NBitXor_1 (i1, i2, o1)
• input 30 i1 input 30 i2
• output 30 o1
• wire n1
• wire 20 n2

• wire n3
• wire 10 n4
• wire n5
• wire n6
• wire n7
• wire n8
• wire n9
• wire 20 n10
• wire n11
• wire n12
• wire 10 n13
• wire n14
• wire n15
• wire n16

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And the Verilog for it (Contd)

• wire n17
• wire n18
• wire 10 n19
• wire 20 n20
• wire 30 n21
• assign n1 i10
• assign n2 i13, i12, i11
• assign n3 n20
• assign n4 n22, n21
• assign n5 n40
• assign n6 n41
• assign n7 n6
• assign n8 i20
• assign n9 n1 n8
• assign n10 i23, i22, i21

• assign n11 n100
• assign n12 n3 n11
• assign n13 n102, n101
• assign n14 n130
• assign n15 n5 n14
• assign n16 n131
• assign n17 n16
• assign n18 n7 n17
• assign n19 n18, n15
• assign n20 n19, n12
• assign n21 n20, n9
• assign o1 n21
• endmodule

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Lessons learned

• Separation of tasks more efficient
• Managing/organizing code
• Intermediate deadlines
• Teamwork/Communication