Combinational MOS Logic Circuit

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Combinational MOS Logic Circuit

• A. Marzuki

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Topics

• Static Characteristic
• Dynamic Characteristic
• Stick Diagram

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Two-Input NOR Gate
VGS,load 0 V
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VOL

• k µCox W/L

for case either Driver are ON,
!VGS VOH
for case both Driver are ON,
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CMOS NOR GATE
Analysis similar to CMOS Inverter , VOL 0 V,
VOHVDD
A
!VS4VDD-VSD3
!ID3ID42ID
B
!replace ID of B with A
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CMOS TG
!Vout is varied. !see current direction for
Source terminal indication
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CMOS TG
EXAMPLE
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Complex Logic Circuits

• OR by parallel-connected drivers.
• AND by series-connected drivers.
• Inversion by MOS circuit operation.

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CMOS Logic Circuit
Pull up graph vertex is drawn with area of pull
down graph. Edge cross pull down graphs edge
once.
Vertex represents node
Pull down graph (NMOS)
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Equivalency
PMOS Gate length increase, NMOS Gate width
increase
CMOS NOR Gate
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Discuss Example 7.2
Assuming W/L for PMOS is 15 for NMOS is 10
Answer is W/L for n is 12, while p is 12.5
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Dynamic Characteristics (Delay)
Capacitance? Pls read chapter 6 and chapter 3.
For our case, We just Use Cout i.e. the final
total capacitance.
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Propagation Delay
Chapter Six
Equivalency
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Stick Diagram

• A stick diagram is a graphical view of a layout.
• Does show all components/vias (except possibly
  tub ties), relative placement.
• Does not show exact placement, transistor sizes,
  wire lengths, wire widths, tub boundaries.

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Stick Diagram

• Represents relative positions of transistors
• Stick diagrams help plan layout quickly
• Need not be to scale
• Draw with color pencils or dry-erase markers

Inverter
NAND2
Out
Out
In
A
B
GND
GND
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Common Euler Path
The Euler path is defined as an uninterrupted
path that traverses each edge (branch) of the
graph exactly once
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Comparison
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References

• S-M. Kang and Y. Leblebici ,CMOS Digital
  Integrated Circuits Analysis and Design,, 3rd
  edition
• Jan M. Rabaey, Anantha Chandrakasan, and Borivoje
  Nikolic, Digital Integrated Circuits A Design
  Perspective, 2nd edition, Prentice Hall, 2002.