Section 4 Fabrication and Layout

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Section 4Fabrication and Layout
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Fabrication- CMOS Process
The Starting Material Preparation 1. Produce
Metallurgical Grade Silicon (MGS) SiO2 (sand)
C in Arc Furnace Si- liquid 98 pure 2.
Produce Electronic Grade Silicon (EGS) HCl
Si (MGS) Successive purification by
distillation Chemical Vapor Deposition (CVD)
3
Fabrication Crystal Growth

• Czochralski Method
• Basic idea dip seed crystal into liquid pool
• Slowly pull out at a rate of 0.5mm/min
• controlled amount of impurities added to melt
• Speed of rotation and pulling rate determine
  diameter of the ingot
• Ingot- 1to 2 meter long
• Diameter 4, 6, 8

4
Fabrication Wafering

• Finish ingot to precise diameter
• Mill flats
• Cut wafers by diamond saw Typical thickness
  0.5mm
• Polish to give optically flat surface

5
Fabrication Oxidation

• Silicon Dioxide has several uses
• - mask against implant
• or diffusion
• - device isolation
• - gate oxide
• - isolation between layers
• SiO2 could be thermally generated
• or through CVD
• Oxidation consumes silicon
• Wet or dry oxidation

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Fabrication Diffusion

• Simultaneous creation of p-n junction over the
• entire surface of wafer
• Doesnt offer precise control
• Good for heavy doping, deep junctions
• Two steps
• Pre-deposition
• Dopant mixed with inert gas introduced in to a
  furnace at 1000 oC.
• Atoms diffuse in a thin layer of Si surface
• Drive-in
• Wafers heated without dopant

wafers
Dopant Gas
Resistance Heater
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Fabrication Ion Implantation

• Precise control of dopant
• Good for shallow junctions and threshold adjust
• Dopant gas ionized and accelerated
• Ions strike silicon surface at high speed
• Depth of lodging is determined by accelerating
  field

8
Fabrication Deposition

• Used to form thin film of Polysilicon, Silicon
  dioxide, Silicon Nitride, Al.
• Applications Polysilicon, interlayer oxide,
  LOCOS, metal.
• Common technique Low Pressure Chemical Vapor
  Deposition (CVD).
• SiO2 and Polysilicon deposition at 300 to 1000
  oC.
• Aluminum deposition at lower temperature-
  different technique

Reactant
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Fabrication Metallization

• Standard material is Aluminum
• Low contact resistance to p-type and n-type
• When deposited on SiO2, Al2O3 is formed good
  adhesive
• All wafer covered with Al
• Deposition techniques
• Vacuum Evaporation
• Electron Beam Evaporation
• RF Sputtering
• Other materials used in conjunction with or
  replacement to Al

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Fabrication Etching

• Wet Etching
• Etchants hydrofluoric acid (HF), mixture of
  nitric acid and HF
• Good selectivity
• Problem
• - under cut
• - acid waste disposal
• Dry Etching
• Physical bombardment with atoms or ions
• good for small geometries.
• Various types exists such as
• Planar Plasma Etching
• Reactive Ion Etching

Plasma
Reactive species
RF
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Fabrication Lithography

• Mask making
• Most critical part of lithography is conversion
  from layout to master mask
• Masking plate has opaque geometrical shapes
  corresponding to the area on the wafer surface
  where certain photochemical reactions have to be
  prevented or taken place.
• Masks uses photographic emulsion or hard surface
• Two types dark field or clear field
• Maskmaking optical or e-beam

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Lithography Mask making
Optical Mask Technique 1. Prepare Reticle
Use projection like system -Precise
movable stage -Aperture of precisely
rectangular size and angular orientation
-Computer controlled UV light source directed to
photographic plate After flashing, plate is
developed yielding reticle
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Fabrication Lithography
Step Repeat
Printing
Printing
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Lithography Mask making

• Electron Beam Technique
• Main problem with optical technique light
  diffraction
• System resembles a scanning electron
  microscope beam blanking and computer
  controlled deflection

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Patterning/ Printing

• Process of transferring mask features to surface
  of the silicon
• wafer.
• Optical or Electron-beam
• Photo-resist material (negative or
  positive)synthetic rubber or
• polymer upon exposure to light becomes
  insoluble ( negative )
• or volatile (positive)
• Developer typically organic solvant-e.g. Xylen
• A common step in many processes is the creation
  and selective
• removal of Silicon Dioxide

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Patterning Pwell mask
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Patterning/ Printing
SiO2
substrate
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Fabrication Steps
Inspect, measure
Post bake
Etch
Develop, rinse, dry
Strip resist
mask
Printer align expose
Deposit or grow layer
Pre-bake
Apply PR
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Fabrication Steps
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Fabrication Steps P-well Process
Diffusion
P
P
Vin
Vo
P well

p
p
n n
p p

n
n
P well
Substrate n-type
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Fabrication Steps P-well Process
VDD
Diffusion
P
P
Vin
Vo
P well

p
p
n n
p p

n
n
P well
Substrate n-type
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Fabrication Steps
n
n
p
p

P well
n
n
p p
P well
Substrate n-type
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Fabrication Steps
Oxidation
oxide
Substrate n-type
Patterning of P-well mask
Substrate n-type
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Fabrication Steps
Diffusion p dopant, Removal of Oxide
P-well
Si3N4
Deposit Silicon Nitride
P-well
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Fabrication Steps
Patterning Diffusion (active) mask
P-well
substrate
FOX
FOX
FOX
Oxidation
substrate
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Fabrication Steps
Thin oxide
FOX
FOX
FOX
Remove Si3N4 Grow thin oxide
P-well
Deposit polysilicon
P-well
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Fabrication Steps
Patterning of Polysilicon
Poly gates
FOX
FOX
FOX
P -well
substrate
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Fabrication Steps
P Layers and n Layer in the Layout
p layer
polysilicon
n layer

P well
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Fabrication Steps
Formation of n and p Diffusion Areas N
Diffusion - Covering with photo-resist -
Patterning of the n layer - Diffusion n
dopant
PR
FOX
FOX
FOX
P-well
n dopant
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Fabrication Steps
Formation of n and p Diffusion Areas P
Diffusion - Cover with photo-resist -
Patterning of the n layer - Diffusion p
dopant
PR
n n
P-well
P dopant
n n
p p
P-well
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Fabrication Steps
p layer
polysilcon
metal
n layer
contact

P well
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Fabrication Steps
SiO2
Strip PR and Deposit Oxide
FOX
FOX
FOX
P-well
Substrate
Patterning of Contact Mask
contact

n n
p p
P-well
Substrate
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Fabrication Steps
Deposit metal layer
Patterning of metal layer
Passivation
FOX
FOX
P-well
Substrate
Deposit Passivation layer
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CMOS 3D Structure
n n
p p
FOX
FOX
FOX
P-well
Substrate (n-type)
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The Bulk Contacts
VDD
n layer
p layer
polysilicon
(substrate)
metal
n layer
contact

p layer
P well
Note Butting contacts provide more
efficient area utilization
GND
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N-Well CMOS
n layer
p layer
metal
N-well
n layer
contact

p layer
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Twin Tub/Double Layer Metal CMOS
Passivation
metal II
Via
Via
SiO2
Metal I
Metal II
FOX
n-wel
l
p-well

Substrate
P well
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Layout Design Rules

• Specifies geometrical constrains on the layout
  art work
• Dictated by electrical and reliability
  constraints with the capability of fabrication
  technology
• Addresses two issues
• reproduction of features on silicon
• interaction between layers
• Main approaches to describe rules
• ? based (scalability)
• absolute

width
spacing
overlap
extension
spacing
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? Based CMOS Design Rules N Well Process
A. N-well
? A.1 Minimum size 10 A.2 Minimum
spacing 6 (Same potential)
A.3 Minimum spacing 8
(Different potentials) B. Active (Diffusion)
B.1 Minimum size 3 B.2 Minimum spacing 3
B.3 N-well overlap of p 5 B.4 N-well
overlap of n 3 B.5 N-well space to n 5
B.6 N-well space to p 3
B35
n
B43
p
B55
n
N-well
B63
B13
p
p
B23
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? Based CMOS Design Rules
C31
C PolyI C.1 Minimum size 2 C.2 Minimum
spacing 2 C.3. Spacing to Active 1 C.4.
Gate extension 2 D. p-plus/n-plus D.1
Minimum overlap of Active 2 D.2 Minimum
size 7 D.3 Minimum overlap of Active 1
in abutting contact D.4. Spacing of
p-plus/n-plus to 3 n/p
gate
C42
C22
C12
D27
D27
active
active
n-plus
p-plus
D12
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? Based CMOS Design Rules
E32
E42
E. Contact E.1 Minimum size 2 E.2
Minimum spacing (Poly) 2 E.3 Minimum
spacing (Active) 2 E.4 Minimum overlap
Active) 2 E.5 Minimum overlap of Poly 2
E.6 Minimum overlap of Metal 1 E.7
Minimum spacing to Gate 2 F. Metal 1 F.1
Minimum size 3 F.2 Minimum spacing 3 G.
Via G.1 Minimum size 3 G.2 Minimum
spacing 3 G.3 Minimum Metal I overlap 1
G.4 Minimum Metal II overlap 1
E12
F23
E61
F13
Metal I
E52
H13
Metal II
G23
H24
G3,G41
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? Based CMOS Design Rules
H. Metal II H.1 Minimum size 3 H.2
Minimum spacing 4 I. Via2 I.1 Minimum
size 2 I.2. Minimum spacing 3 J. Metal
III J.1 Minimum size 8 J.2. Minimum
spacing 5 J.3 Minimum Metal II overlap 2 K.
Passivation K.1 Minimum opening 100m
K.2 Minimum spacing 150m
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Layout of a CMOS Inverter ? Based Design Rules
N-well
C1
B3
p-plus
B4
n-plus
E6
Active
Via
Metal II
G1
p-plus
n-plus
E4
D1
metalI
C4
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Stick Diagram Notation

• It helps to visualize the function as well as
  topology
• It helps in floor planning
• 4 layers for SLM Poly, diffusion, metal,
  contact
• 6 layers for DLM Poly, Diffusion, Metal I,
  Metal II, Contact, Via
• Construction Guidelines
• When two wires of the same color intersects
  or touch, they are
  electrically connected.
• Contacts represented by (X) and via by (? )
• When poly crosses diffusion, a transistor is
  formed
• PMOS transistors identified by a small circle
  around the poly-diffusion intersection

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Stick Diagram Notation
VDD
Vout
Vin
GND
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Mixed Notation
C
B
A
C
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Standard Cells

• Modularized approach for layout
• Follows certain guidelines in designing these
  modules
• Each module represents a basic combinational or
  sequential logic function.
• Each module has a standard height and variable
  width referred to as Standard Cell
• A collection of these cells referred to as a
  Standard Cell Library
• ASIC Designers deal with abstracted
  representation of these cells to construct a
  complete design
• The abstracted representation is referred to as
  the Foot Print
• Each abstracted representation consists of input
  and output terminals referred to as I/O Ports

Foot Print
Cell Name
I/O ports
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Standard Cells


Output port
Input port
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Standard Cells

Output Port
Input Port
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Standard Cells
For DLM process, vertical routes use metal II.
Horizontal routes use Metal I Notice the
connections between Metal I and Metal II For
Multi-level metal processes cell rows are flipped
and butted. Routing can be made on top of the
cell rows
Routing Channel
(More to come in section 5)
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Yield Analysis
Yield is defined as Number of Good
chips on wafer X 100 Total Number of
chips Influenced by Defect density
Chip area Design rule lithography
dimensions Number of mask levels Defects
Crystal defects film deposition and growth
defects photo-resist imperfections
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Yield Analysis
Models 1. Seeds model for large chips
and low yields
A chip area D defect density 2.
Murphys model for small chips and high yields