Design Automation Conference

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VLSI Design Using PC-Based Tools

• Cherrice Traver
• Union College
• Schenectady, NY

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Why use PC-based tools?
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Outline

• Tanner Research Tools for Education
• Practical issues
• Tool flow and capabilities
• Example use
• Curriculum examples

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Practical Issues System Requirements

• Minimum requirements
• 100 MHz PCs, 32M RAM
• Recommended
• 500 MHz PCs, 256M RAM
• 3-button mouse

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Practical IssuesInstallation

• Tool installation - Install-Shield Wizard
• License server
• Sentinel LM on NT Server
• Floating individual tool licenses

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Practical IssuesTool Choices
L-Edit
DRC EXT SPR
L-Edit Pro
CMOS Libraries
Tspice S-Edit W-Edit
T-Spice Pro
Design Pro
Tanner Tools Pro
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Practical Issues Cost and Maintenance

• Educational pricing
• Quantity pricing
• Free support for 60 days
• No annual maintenance fee required
• 15 maintenance fee per year for updates and
  continued support

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Practical IssuesDocumentation

• Help Menu Indexed PDF Manual

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Contact Information

• Janice Barthelemy
• Account Manager
• janice_at_tanner.com

Tanner EDA 2650 East Foothill Blvd. Pasadena, CA
91107
Toll free [phone] Fax (626)
792-0300 www.tanner.com
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Simplified Tanner Tool Flow
S-Edit TM Schematic Editor
T-Spice TM Circuit Simulator
W-Edit TM Waveform Viewer
L-Edit TM Full Custom Layout Editor
GDS II CIF
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Overview of Examples

• Layout Editor - L-Edit
• Schematic Editor - S-Edit
• Standard Cell Place and Route - SPR
• Spice simulator - T-Spice

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L-Edit Tool Flow
S-Edit TM
T-Spice TM
L-Edit/SPR TM Standard Cell Place Route
L-Edit/Extract TM General Device Extractor
Layout Libraries SCMOSLib ...
L-Edit TM Full Custom Layout Editor
L-Edit/DRC TM On-line Design Rule Checker
Cross Section Viewer
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L-Edit Layout Editor Features
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L-Edit Example

• CMOS Inverter
• Layout Editing
• DRC
• Cross Section Viewing
• Extract Spice File

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S-Edit Tool Flow
Technology Mapping Library SCMOS ...
S-Edit TM Schematic Editor
SchemLib TM Technology Independent Library
netlist extract
T-Spice TM
NetTran
SPR
L-Edit TM
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S-Edit Schematic Editor Features
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S-Edit Example

• Full Adder Circuit
• Schematic Drawing
• Spice Export
• Tanner Place and Route Export

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SPR Tool Flow
S-Edit TM
.tpr file
L-Edit/SPR TM Standard Cell Place Route
Layout Libraries SCMOSLib ...
L-Edit TM Full Custom Layout Editor
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SPR Example

• Full Adder Circuit
• L-Edit - Place and Route
• Core Padframe
• Extract Spice Circuit

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T-Spice and W-edit Tool Flow
S-Edit TM
netlist extract
T-Spice TM Circuit Simulator
W-Edit TM Waveform Viewer
device extract
L-Edit TM
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T-Spice and W-edit Features

• Menu-based command insertion
• Integrated W-Edit waveform viewer
• Circuit Probing from S-Edit

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T-Spice and W-edit Example

• Full Adder simulation
• Simulation of schematic netlist
• Waveform probing
• Simulation of extracted layout

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Tool Integration in VLSI Design Course

• Laboratories
• Tool use
• Reinforcement of lecture topics
• Project
• Behavior --gt Layout design experience

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Laboratories

• Lab 1 - L-Edit/T-Spice
• Extract/simulate NAND gate
• Layout/extract/simulate inverter
• Lab 2 - L-Edit/T-Spice
• Manual placement/routing standard cells
• Manual stick diagrams
• Extraction/simulation
• Lab 3 - S-Edit/L-Edit/SPR/T-Spice
• Schematic capture - netlist simulation
• Standard cell place/route

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Kitchen Timer Projectfrom Modern VLSI Design
Systems on Silicon, Wayne Wolf
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Buzz Circuit

• Schematic Given - Lab Exercise

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Display Circuit

• Block Diagram Given - Lab Exercise

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Controller

• Specified by state diagram and VHDL model
• Logic simulation outputs provided

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Timer
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Support Provided

• VHDL Golden behavioral model
• Simulation output results
• Lots of guidance on debugging

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Top Level Schematic
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Kitchen Timer Chip Statistics

• 600 Gates
• 8000 Transistors
• Layout area 1550 um x 1375 um

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Final Layout
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MOSIS Fabrication

• Pads provided
• Flatten layout
• Export CIF file

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Other Past DesignsUsing Tanner Tools

• Quadrature Decoder
• http//doc.union.edu/154/Quad.decode.project/index
  .html
• Simple Floating-Point Multiplier
• http//doc.union.edu/154/Mult.project/mult.project
  .html

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Conclusion

• Ease of Installation/Maintenance
• Reasonable Design Flow
• Good Interface for MOSIS Fabrication