Packaging and Interconnection

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Packaging and Interconnection
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References

• H.B.Bakoglu, Circuits, Interconnections, and
  Packaging for VLSI, Addison-Wesley, 1990

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• Packaging

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• 1. Overview
• Agony of interconnection
• Device becomes smaller, faster while chip size
  and routing length becomes bigger.
• IR voltage drop, delay, power dissipation due to
  interconnects, and max. current density, noise
  coupling/crosstalk are serious problems in future
  VLSI and now.
• Typical distribution of interconnection lines.

Clock, bus
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• Multi-level interconnection

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• 2. Packaging
• Package Types 2-side DIP(Dual In-Line)
  thru-hole
• 4-side QFP(Quad Flat Package) SMT
  (Surface
• Mount
  Tech.)
• area type PGA(Pin Grid Array) thru-hole
• BGA(Ball Grid Array)
• Chip to package bonding wire bonding
• TAB (Tape Automated Bonding)
• Flip-chip bonding

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• MCN(Multi-Chip Module)

Level 0
Level 1
Level 2
Level 3
Level 15
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• MCM ??? ?? ? ??
• MCM-L(Laminated)
• ??? ???? PCB ??, ??, ???, Cache ??? ?? ? ??? ??
• MCM-C(Ceramic)
• ????? ??, ?? ???, ??/??? ????
• MCM-D(Deposited)
• ??? ? ?????? ??, ??/????? ????, ???, ????,
  Workstation, PC, ????? ? ???? ??

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• MCM ?? ??
• MCM ?? ??
• ????, ??? ??, ????, PCB ?? ? ???? (??, ??), ???
  ?? ??(??), ?? ?? ??(??)
• MCM ???? ??
• coating, etching, metallization, lithography ?
• ??? ??(bare)? ?? ??
• Known Good Die(KGD) ?? MCM Yield
• MCM ??? ??
• Inter-disciplinary collaboration

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• MCM ?? ? ?? ??(1997 ?? ??)
• 1998? MCM ?? 1.6 billion
• MCM ??? ? driver
• ??? ??, ?? ??(B-ISDN) (HDTV, CATV, ATM ?)
• ??? ???? (DSP, GPS, RISC ?), Workstation/PC,
  ?????
• ??? MCM-L ??
• ?? PCB? ??
• ??? MCM-D ?? gt 100MHz

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• Multi-Chip Module Technique
• ??
• i) IC ? ? ? ??? ? ??
• ii) Substrate (?????(TCE), ????, ? ???, ??)
• type
• MCM-L FR-4, Polyimide Glass,
• MCM-D Si, SiC, SiN, SiO2
• MCM-C Alumina,
• Hybrid MCM
• Routing ???, I/O ??, ? ??, ??? ??(via ??)
• ???? ?? - ???
• ?? - ??(Cr/Cu-Polymer-Cu-Polymer-Cu/Au)-chip
• ??
• i) ? bonding(die bonding)
• ii) ?? ?? ?? wire bonding, TAB, flip chip
• ??? ??

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• MCM Package Structures
• Technology Thin Film Thick Film PCB
• (type) (MCM-D) (MCM-C) (MCM-L)
• A. Dielectric Polyimide/SiO2 Alumina Epoxy-Glass
• GlassCeramic Polyimide-glass
• Dielectric Constant Er 3.2/3.8 9-10/4-8 4.7/2.5
• Resistivity(?-cm) 1016/1014 1014/1014 1014/1014
• Thickness(?m) lt 20 100 and up 100 and up
• B. Conductors Cu-Al W, Mo, Cu, Au Cu, Au
• Sheet resistance(m?/sq) 3-4.2 2-15 3
• Thickness(?m) 10 20-30 18-35
• Line width(?m) 25 100 and up 70 and up
• Via hole size(?m) 40 100 and up 50 and up
• Min Via Grid(?m) 100 250 and up 250 and up
• No. of Layers 1-6 30 and up 50
• C. Dielectric and Via
  Coat/DepositLitho Tape/Punch Punch/Drilling
• D. Conductor Sputter Screen Laminate/Deposit
• electroplate,Photoli
  tho
• E. Firing/Curing/Arm 400 C(Oxidizing) 900C(N2) lt
  100C

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• MCM design flow
• Chip placement
• wiring design
• i) of I/O ports, module area, wire
  length/layer, via
• Chip placement
• Electrical considerations
• Electrical Design Considerations
• a) Key design factors
• 1. Physical dimension(space)
• 2. Electrical consideration
• 3. Thermal consideration
• b)Information transfer process
• 1. Change in the signal level
• 2. Signal transition time
• c)Electrical parameters Requirements
• R- Voltage drops Faster switching speeds
• C- RC delays Reducing input capacitance
• L- delay noise Optimizing the driving
  impedance

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• Module Package - MCM-C Package

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• MCM-C Cross-section

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• Interconnection Modelling as a Transmission Line

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Interconnection Modelling

• Modelling of interconnection line as
• i) lumped C model treated as lumped capacitive
• loads
• ii) lumped RC mode first-order consideration
  of
• R when R is
  significant
• iii) distributed RC model better consideration
  of
• Rs (intra-chip
  wire)
• iv) transmission line model if the
  interconnection wire is sufficiently long or
  circuits very fast s.t. signal rise time is
  comparable to the time of flight across the line,
  i.e, L is not negligible.(PCB wire)
• v) lossy transmission line model (MCB
  substrate wire)

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• Interconnection wire? ??? modelling
• l wire length
• ? signal ? wavelength
• tl/v time of flight
• t?/v signal ? rise time
• 1. t ltlt Tr (i.e., l ltlt ?)? ??
• wire? lumped capacitance? model ??
• 2. ??? ?? ??
• 1) lossless ? ? (R ??? L ??? ?? ?? ?)
• transmission line?? model
• 2) lossy ? ??
• R ??? L ???? ??? Transmission line?? ??? RC
  distributed ??? model ??. ?, wire R gtgt
  Zo(????)?
• ??

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• Observations
• 1. High-speed chip? detailed modelling? ????
  pin, lead frame, bonding wire ?? ????? ?? 2-D ???
  ?? ?.
• 2. ??? chip-to-chip delay ??? ???? board wiring?
  ?????, pin, lead frame ?? lumped C or L load?
  model ?? ??.
• 3. Power ground line? Signal line? ?? C? ??? L?
  ??? ?? ??.
• ( ??? noise)

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Transmission line model

• Lossless transmission line
• Inductance of a device

V
B
A
I
?
I
D
C
Magnetic flux
Electric current carried
(L and ? are inductance, and magnetic flux
per line length.)
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• Similarly for C

Zo(char imp)
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• Reflected waveforms for inductive capacitive
  discontinuity (time constant L/2Z, ZC/2)

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• Magnitudes of Reflected Transmitted components
  of voltage(current) wave at the transmission line
  discontinuity.

Ii
Ir
It
Vi
Vr
Vt
Z1
Z2
Vi
Vr
Vt
Define ?(reflection coeff.) and
T(transmission coeff.)
Then, from(1), T 1 ? and from(2),
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• Reflected waveforms at the unterminated
  transmission line

VVS /2
V-source? ?? VG? ?? ?? R-divider? ? ?? VVS?,
X-mission line?? ? ?? VVS /2? ???.
RS0.1 Z??
RS10 Z??
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• When Rs10Z, RsZ, and Rs0.1Z, respectively(not
  in the same scale)

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• Waveforms for finite rise-time signal

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• Waveform propagating along lossy transmission
  line.

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• Transmission line? termination
• i) RS0, RL?(no termination) (dotted line
  RS0.1 Zo ??)

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• ii) Term. at receiving end (RS0, RLZo)

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• iii) Source-end termination

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• v) RC-termination at receiving end RS0,
  RLZo(CLgtgt )

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iv) ??
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• Driver and termination circuits for tr. lines.
• i) term. at receiver end

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• ii) term. at the source end(series termination)

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What limits bandwidth?

• Circuit speed
• Impedance discontinuity
• Pad capacitance
• Bonding wire
• Package trace
• PCB trace
• PLL DLL jitter in the receiver
• Wire limits

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Copper vs Fiber

• Copper
• Coaxial Cable, Twin-axial Cable, UTP (unshielded
  Twisted Pair), STP (Shielded Twisted Pair), etc.
• High bandwidth over short distance
• Low cost
• EMI, ground isolation, interference problem
• Fiber
• Multi-mode fiber (Step-index, Graded-index),
  Single-mode fiber
• Light sources Laser diode or LED
• Material Silica or plastic
• High bandwidth over long distance
• High cost
• No interference, no crosstalk, no EMI
• Interface with electrical signals through a
  limiting amplifier (TX) and a trans-resistance
  amplifier (RX)

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Basic Electrical Problem over Wire

• Transmitter
• convert bits to an analog voltage
• Channel (Wire)
• propagate the voltage/current
• Receiver
• convert the analog voltage to bits

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Signal Reflection Wave Diagram
RS
Z0
VS
RL
V1
Z0
V1 VS
RL - Z0
V1-
RS Z0
V1- V1
RL Z0
RS - Z0
V2
V2- V1-
RS Z0
V2-
V1
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Unterminated Line
td
ZO
P
VS
VS
td
2td
at P
VS
0
td/2
3td/2
5td/2
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Parallel Termination
td
RL ZO
ZO
P
VS
VS
td
2td
VS
at P
0
td/2
3td/2
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Series Termination
open
td
RS ZO
ZO
P
VS/2
VS
td
VS
2td
VS/2
VS
at P
0
td/2
3td/2
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Conclusion

• Signal reflection at discontinuity points
• Signal rise time must be longer than travel time
  for justifying lumped element analysis, otherwise
  transmission line modelling is necessary.